Add cyc1000 target

data/cyc1000.sdc

@@ -0,0 +1,8 @@
+# Main system clock (12 Mhz)
+create_clock -name "clk" -period 83.333ns [get_ports {i_clk}]
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty

data/cyc1000.tcl

@@ -0,0 +1,14 @@
+#
+# Clock / Reset
+#
+set_location_assignment PIN_M2 -to i_clk
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_clk
+set_location_assignment PIN_N6 -to i_rst
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_clk
+
+#UART/GPIO
+set_location_assignment PIN_M6 -to q
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to q
+
+set_location_assignment PIN_T7 -to uart_txd
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart*

servant.core

@@ -31,6 +31,13 @@ filesets:
     file_type : verilogSource
     depend : [serv]
 
+  cyc1000:
+    files:
+      - data/cyc1000.sdc : {file_type : SDC}
+      - data/cyc1000.tcl : {file_type : tclSource}
+      - servant/servclone10_clock_gen.v : {file_type : verilogSource}
+      - servant/servclone10.v : {file_type : verilogSource}
+
   tinyfpga_bx: {files: [data/tinyfpga_bx.pcf : {file_type : PCF}]}
   icebreaker : {files: [data/icebreaker.pcf  : {file_type : PCF}]}
   verilator_tb: {files: [bench/servant_tb.cpp : {file_type : cppSource}]}
@@ -48,6 +55,17 @@ targets:
   default:
     filesets : [soc]
 
+  cyc1000:
+    default_tool: quartus
+    description: cyc1000 FPGA board
+    filesets : [mem_files, soc, cyc1000]
+    parameters : [memfile, memsize=32768]
+    tools:
+      quartus:
+        family : Cyclone 10 LP
+        device : 10CL025YU256C8G
+    toplevel : servclone10
+
   icebreaker:
     default_tool : icestorm
     filesets : [mem_files, soc, service, icebreaker]

servant/servclone10.v

@@ -0,0 +1,31 @@
+`default_nettype none
+module servclone10
+(
+ input wire 	   i_clk,
+ input wire 	   i_rst,
+ output wire 	   q,
+ output wire 	   uart_txd);
+
+   parameter memfile = "zephyr_hello.hex";
+   parameter memsize = 8192;
+
+   wire      wb_clk;
+   wire      wb_rst;
+
+   assign uart_txd = q;
+
+   servclone10_clock_gen clock_gen
+     (.i_clk (i_clk),
+      .i_rst (i_rst),
+      .o_clk (wb_clk),
+      .o_rst (wb_rst));
+
+   servant
+     #(.memfile (memfile),
+       .memsize (memsize))
+   servant
+     (.wb_clk (wb_clk),
+      .wb_rst (wb_rst),
+      .q      (q));
+
+endmodule

servant/servclone10_clock_gen.v

@@ -0,0 +1,50 @@
+`default_nettype none
+module servclone10_clock_gen
+  (input wire i_clk,
+   input wire i_rst,
+   output wire o_clk,
+   output wire o_rst);
+
+   wire [4:0]  clk;
+
+   wire        clk_fb;
+
+   wire        locked;
+   reg [9:0]   r;
+
+   assign o_clk = clk[0];
+
+   assign o_rst = r[9];
+
+   always @(posedge o_clk)
+     if (locked)
+       r <= {r[8:0],1'b0};
+     else
+       r <= 10'b1111111111;
+
+   cyclone10lp_pll
+     #(.bandwidth_type         ("auto"),
+       .clk0_divide_by         (6),
+       .clk0_duty_cycle        (50),
+       .clk0_multiply_by       (16),
+       .clk0_phase_shift       ("0"),
+       .compensate_clock       ("clk0"),
+       .inclk0_input_frequency (83333),
+       .operation_mode         ("normal"),
+       .pll_type               ("auto"),
+       .lpm_type               ("cyclone10lp_pll"))
+   pll
+     (.activeclock   (),
+      .areset        (i_rst),
+      .clk           (clk),
+      .clkbad        (),
+      .fbin          (clk_fb),
+      .fbout         (clk_fb),
+      .inclk         (i_clk),
+      .locked        (locked),
+      .phasedone     (),
+      .scandataout   (),
+      .scandone      (),
+      .vcooverrange  (),
+      .vcounderrange ());
+endmodule