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42 Commits 11 Branches 9 Tags
Commit Graph

10 Commits

Author SHA1 Message Date
Olof Kindgren
12039dec0e Add support for setting memory contents during synthesis 2018-11-26 09:49:08 +01:00
Olof Kindgren
a974320f46 Further optimizations 2018-11-23 21:26:49 +01:00
Olof Kindgren
1bbf8e3ce9 Synthesis fixes 2018-11-22 20:58:45 +01:00
Olof Kindgren
9df2a0060b Use custom interconnect. Runs on hw 2018-11-21 13:15:33 +01:00
Olof Kindgren
6e034361d4 Add UART decoder 2018-11-19 09:42:42 +01:00
Olof Kindgren
ff63519607 Temporary hack to blink LED on tinyfpga BX 2018-11-18 21:42:42 +01:00
Olof Kindgren
7666ac4092 synthesized netlist works 2018-11-18 13:05:38 +01:00
Olof Kindgren
d4102f927f Synthesis fixes 2018-11-17 22:14:44 +01:00
Olof Kindgren
f66f82a57a Add explicit wire defs to ports 2018-11-17 21:30:03 +01:00
Olof Kindgren
a92c933af1 csr, verilator, traps 2018-11-14 12:16:20 +01:00