Olof Kindgren
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079d973969
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Cleanup
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2018-11-21 13:22:55 +01:00 |
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Olof Kindgren
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9df2a0060b
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Use custom interconnect. Runs on hw
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2018-11-21 13:15:33 +01:00 |
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Olof Kindgren
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6e034361d4
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Add UART decoder
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2018-11-19 09:42:42 +01:00 |
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Olof Kindgren
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ff63519607
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Temporary hack to blink LED on tinyfpga BX
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2018-11-18 21:42:42 +01:00 |
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Olof Kindgren
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2062d084bf
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Disable GPIO output in verilator
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2018-11-18 21:40:51 +01:00 |
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Olof Kindgren
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7666ac4092
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synthesized netlist works
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2018-11-18 13:05:38 +01:00 |
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Olof Kindgren
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d4102f927f
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Synthesis fixes
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2018-11-17 22:14:44 +01:00 |
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Olof Kindgren
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0362192769
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Use internal reset
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2018-11-17 22:06:10 +01:00 |
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Olof Kindgren
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f66f82a57a
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Add explicit wire defs to ports
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2018-11-17 21:30:03 +01:00 |
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Olof Kindgren
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a92c933af1
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csr, verilator, traps
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2018-11-14 12:16:20 +01:00 |
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Olof Kindgren
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3c98d35766
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Change to wb interface
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2018-11-09 21:26:13 +01:00 |
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Olof Kindgren
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8409aa4c4b
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lh, lw, lbu, lhu, sb, sh, slti
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2018-11-01 22:51:51 +01:00 |
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Olof Kindgren
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96b1906676
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bne, srai
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2018-10-30 22:41:05 +01:00 |
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Olof Kindgren
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c2030a95fd
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jal, addi, lui, lb
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2018-10-26 22:52:39 +02:00 |
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Olof Kindgren
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e10c41be8d
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Initial commit
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2018-10-23 23:45:41 +02:00 |
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