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2 Commits

Author SHA1 Message Date
Gwenhael Goavec-Merou
d90030b955 xilinx PLL: allows to specify PLL output frequency (16 or 32 MHz) 2019-11-10 21:44:50 +01:00
Olof Kindgren
4b371c533f Add nexys a7 support 2019-06-24 13:18:34 +02:00