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36 lines
759 B
Verilog
36 lines
759 B
Verilog
`default_nettype none
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module servant_cmod_a7_clock_gen
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(input wire i_clk,
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input wire i_rst,
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output wire o_clk,
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output reg o_rst);
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wire clkfb;
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wire locked;
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reg locked_r;
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MMCME2_BASE
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#(.CLKIN1_PERIOD (83.333), //12MHz
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/* Set VCO frequency to 12*64=768 MHz
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Allowed values are 2.0 to 64.0. Resulting VCO freq
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needs to be 600-1200MHz */
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.CLKFBOUT_MULT_F (64.000),
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.CLKOUT0_DIVIDE_F (48.000)) // 768/48 = 16 MHz
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pll
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(.CLKIN1 (i_clk),
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.RST (i_rst),
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.CLKOUT0 (o_clk),
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.LOCKED (locked),
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.CLKFBOUT (clkfb),
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.CLKFBIN (clkfb));
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always @(posedge o_clk) begin
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locked_r <= locked;
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o_rst <= !locked_r;
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end
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endmodule
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`default_nettype wire
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