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41 lines
814 B
Verilog
41 lines
814 B
Verilog
`default_nettype none
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module servix_clock_gen
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(input wire i_clk,
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input wire i_rst,
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output wire o_clk,
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output reg o_rst);
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parameter frequency = 32;
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wire clkfb;
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wire locked;
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reg locked_r;
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PLLE2_BASE
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#(.BANDWIDTH("OPTIMIZED"),
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.CLKFBOUT_MULT(16),
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.CLKIN1_PERIOD(10.0), //100MHz
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.CLKOUT0_DIVIDE((frequency == 32) ? 50 : 100),
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.DIVCLK_DIVIDE(1),
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.STARTUP_WAIT("FALSE"))
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PLLE2_BASE_inst
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(.CLKOUT0(o_clk),
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.CLKOUT1(),
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.CLKOUT2(),
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.CLKOUT3(),
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.CLKOUT4(),
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.CLKOUT5(),
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.CLKFBOUT(clkfb),
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.LOCKED(locked),
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.CLKIN1(i_clk),
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.PWRDWN(1'b0),
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.RST(i_rst),
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.CLKFBIN(clkfb));
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always @(posedge o_clk) begin
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locked_r <= locked;
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o_rst <= !locked_r;
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end
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endmodule
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