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21 lines
470 B
Verilog
21 lines
470 B
Verilog
`default_nettype none
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module serv_sleep
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(
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input wire i_clk,
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input wire i_rst,
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input wire i_timer_irq,
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input wire i_external_irq,
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input wire i_cnt0,
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input wire i_wfi,
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input wire i_init,
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input wire i_mtie,
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input wire i_meie,
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output wire o_sleep_req,
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output wire o_wakeup_req);
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assign o_sleep_req = i_wfi & i_cnt0 & i_init;
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assign o_wakeup_req = (i_timer_irq & i_mtie) | (i_external_irq & i_meie);
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endmodule
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