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24 lines
376 B
Verilog
24 lines
376 B
Verilog
`default_nettype none
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module serv_top_tb;
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parameter memfile = "bitbang.hex";
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reg wb_clk = 1'b1;
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reg q_r = 1'b0;
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wire q;
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always #31 wb_clk <= !wb_clk;
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vlog_tb_utils vtu();
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serv_wrapper #(memfile) dut(wb_clk, q);
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always @(posedge wb_clk)
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if (q != q_r) begin
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$display("%0t : q is %s", $time, q ? "ON" : "OFF");
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q_r <= q;
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end
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endmodule
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