Florian Zaruba 27621a285e rtl: Make compatible to Synopsys Design Compiler ...

Synopysis DC has problems with forward references and initial
statements. Fixed that for better compatibility.

2019-09-26 22:57:40 +02:00

..

ser_add.v

Use custom interconnect. Runs on hw

2018-11-21 13:15:33 +01:00

ser_lt.v

Fix bugs and missing resets to pass formal

2018-12-11 22:05:32 +01:00

ser_shift.v

Reduce warnings

2019-06-24 15:22:08 +02:00

serv_alu.v

Simplify alu_cmp_eq control logic

2019-07-23 12:10:38 +02:00

serv_bufreg.v

Remove bytepos from serv_mem_if

2019-09-16 00:07:58 +02:00

serv_csr.v

Separate state and decode from CSR signals

2019-09-14 22:18:03 +02:00

serv_ctrl.v

Pass imm offsets through bufreg

2019-09-13 23:30:46 +02:00

serv_decode.v

Avoid exposing funct3 from decode

2019-09-15 23:50:02 +02:00

serv_mem_if.v

Set o_dbus_we directly from decode

2019-09-16 00:13:21 +02:00

serv_mpram.v

rtl: Make compatible to Synopsys Design Compiler

2019-09-26 22:57:40 +02:00

serv_params.vh

Simplify csr stuff

2019-09-13 23:30:46 +02:00

serv_regfile.v

Add SERV_CLEAR_RAM parameter

2019-06-24 13:18:34 +02:00

serv_state.v

Remove unused rs_en signal

2019-09-16 10:45:42 +02:00

serv_top.v

rtl: Make compatible to Synopsys Design Compiler

2019-09-26 22:57:40 +02:00

shift_reg.v

rtl: Make compatible to Synopsys Design Compiler

2019-09-26 22:57:40 +02:00