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27 lines
586 B
Verilog
27 lines
586 B
Verilog
`default_nettype none
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module riscv_timer
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(input wire i_clk,
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input wire i_rst,
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output reg o_irq = 1'b0,
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input wire [31:0] i_wb_dat,
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input wire i_wb_we,
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input wire i_wb_cyc,
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output wire [31:0] o_wb_dat);
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reg [15:0] mtime;
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reg [15:0] mtimecmp;
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assign o_wb_dat = mtime;
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always @(posedge i_clk) begin
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if (i_wb_cyc & i_wb_we)
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mtimecmp <= i_wb_dat;
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mtime <= mtime + 16'd1;
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o_irq <= (mtime >= mtimecmp);
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if (i_rst) begin
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mtime <= 16'd0;
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mtimecmp <= 16'd0;
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end
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end
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endmodule
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