mirror of
https://github.com/olofk/serv.git
synced 2026-01-13 07:09:33 +00:00
42ac1e5e4d
Since FPGA uses fixed-size RAM, it's better in most cases to store the CSR in unused memory positions in that RAM. Since the decoding is made more complex, the old register file implementation is kept around since that is more efficient when we don't want CSR and potentially when the FPGA support hardware shift registers.
175 lines
3.8 KiB
Plaintext
175 lines
3.8 KiB
Plaintext
CAPI=2:
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name : ::serv:0
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filesets:
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core:
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files:
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- rtl/serv_params.vh : {is_include_file : true}
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- rtl/shift_reg.v
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- rtl/ser_add.v
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- rtl/ser_lt.v
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- rtl/ser_shift.v
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- rtl/serv_bufreg.v
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- rtl/serv_alu.v
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- rtl/serv_csr.v
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- rtl/serv_ctrl.v
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- rtl/serv_decode.v
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- rtl/serv_mem_if.v
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- rtl/serv_regfile.v
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- rtl/serv_mpram.v
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- rtl/serv_top.v
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file_type : verilogSource
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ice40_pll:
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files:
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- rtl/ice40_pll.v : {file_type : verilogSource}
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depend : ["fusesoc:utils:generators"]
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mem_files:
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files:
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- sw/blinky.hex : {copyto : blinky.hex}
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- sw/zephyr_hello.hex : {copyto : zephyr_hello.hex}
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file_type : user
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serv_top_tb:
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files:
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- bench/serv_top_tb.v
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file_type : verilogSource
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depend : [vlog_tb_utils]
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wrapper:
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files:
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- rtl/serv_clock_gen.v
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- rtl/riscv_timer.v
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- rtl/wb_gpio.v
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- bench/serv_arbiter.v
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- bench/serv_mux.v
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- bench/serv_wrapper.v
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file_type : verilogSource
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depend : [wb_ram]
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netlist:
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files: [synth.v : {file_type : verilogSource}]
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tinyfpga_bx:
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files:
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- data/tinyfpga_bx.pcf : {file_type : PCF}
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icebreaker:
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files:
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- data/icebreaker.pcf : {file_type : PCF}
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verilator_tb:
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files:
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- bench/serv_soc_tb.cpp : {file_type : cppSource}
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targets:
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default:
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filesets : [core]
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icebreaker:
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default_tool : icestorm
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filesets : [core, ice40_pll, mem_files, wrapper, icebreaker]
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generate: [icebreaker_pll]
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parameters : [memfile, memsize, PLL=ICE40_PAD]
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tools:
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icestorm:
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nextpnr_options: [--up5k, --freq, 16]
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pnr: next
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toplevel : serv_wrapper
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synth:
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default_tool : icestorm
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filesets : [core, mem_files, wrapper, tinyfpga_bx]
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toplevel : serv_wrapper
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tinyfpga_bx:
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default_tool : icestorm
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filesets : [core, ice40_pll, mem_files, wrapper, tinyfpga_bx]
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generate: [tinyfpga_bx_pll]
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parameters : [memfile, memsize, PLL=ICE40_CORE]
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tools:
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icestorm:
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nextpnr_options : [--lp8k, --package, cm81, --freq, 32]
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pnr: next
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toplevel : serv_wrapper
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lint:
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default_tool : verilator
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filesets : [core]
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tools:
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verilator:
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mode : lint-only
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toplevel : serv_top
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serv_top_tb:
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default_tool: icarus
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filesets : [core, wrapper, serv_top_tb]
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parameters : [RISCV_FORMAL=true, firmware]
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toplevel : serv_top_tb
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synth_tb:
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default_tool: icarus
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filesets : [netlist, serv_top_tb]
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toplevel : serv_top_tb
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verilator_tb:
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default_tool: verilator
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filesets : [core, wrapper, verilator_tb]
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parameters : [RISCV_FORMAL, firmware, memsize, signature, uart_baudrate, vcd]
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tools:
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verilator:
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verilator_options : [--trace]
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toplevel : serv_wrapper
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parameters:
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PLL:
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datatype : str
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description : PLL type to use for main clock generation
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paramtype : vlogparam
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RISCV_FORMAL:
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datatype : bool
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paramtype : vlogdefine
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firmware:
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datatype : file
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description : Preload RAM with a hex file at runtime (overrides memfile)
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paramtype : plusarg
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memfile:
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datatype : file
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description : Preload RAM with a hex file at compile-time
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paramtype : vlogparam
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memsize:
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datatype : int
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default : 8192
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description : Memory size in bytes for RAM (default 8kiB)
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paramtype : vlogparam
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signature:
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datatype : file
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paramtype : plusarg
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uart_baudrate:
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datatype : int
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description : Treat q output as an UART with the specified baudrate (0 or omitted parameter disables UART decoding)
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paramtype : plusarg
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vcd:
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datatype : bool
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paramtype : plusarg
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generate:
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icebreaker_pll:
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generator: icepll
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parameters:
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freq_out : 16
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tinyfpga_bx_pll:
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generator: icepll
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parameters:
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freq_in : 16
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freq_out : 32
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