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Store CSR in RF RAM
Since FPGA uses fixed-size RAM, it's better in most cases to store the CSR in unused memory positions in that RAM. Since the decoding is made more complex, the old register file implementation is kept around since that is more efficient when we don't want CSR and potentially when the FPGA support hardware shift registers.
This commit is contained in:
Olof Kindgren
parent
b0a062ae21
commit
42ac1e5e4d
@ -4,13 +4,16 @@ module serv_csr
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input wire i_clk,
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input wire [4:0] i_cnt,
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input wire [3:0] i_cnt_r,
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//From mpram
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input wire i_rf_csr_out,
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//to mpram
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output wire o_csr_in,
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//Stuff
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input wire i_mtip,
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output wire o_timer_irq_en,
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input wire i_mstatus_en,
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input wire i_mie_en,
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input wire i_mtvec_en,
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input wire i_mip_en,
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input wire i_mscratch_en,
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input wire i_mepc_en,
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input wire i_mcause_en,
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input wire i_mtval_en,
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@ -38,16 +41,13 @@ module serv_csr
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reg mstatus;
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reg mstatus_mie;
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reg mie_mtie;
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reg [31:0] mtvec = 32'h0;
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reg [31:0] mscratch;
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reg [31:0] mepc;
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reg mcause31;
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reg [3:0] mcause3_0;
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wire mcause;
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reg [31:0] mtval;
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wire csr_in;
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wire csr_out;
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@ -58,8 +58,7 @@ module serv_csr
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1'bx;
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assign csr_out = (i_mstatus_en & mstatus) |
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(i_mtvec_en & mtvec[0]) |
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(i_mscratch_en & mscratch[0]) |
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i_rf_csr_out |
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(i_mepc_en & mepc[0]) |
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(i_mcause_en & mcause) |
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(i_mtval_en & mtval[0]);
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@ -72,6 +71,8 @@ module serv_csr
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((i_cnt[4:2] == 3'd7) & i_cnt_r[3]) ? mcause31 //[31]
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: 1'b0;
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assign o_csr_in = csr_in;
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always @(posedge i_clk) begin
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if (i_mstatus_en & (i_cnt[4:2] == 3'd0) & i_cnt_r[3])
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mstatus_mie <= csr_in;
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@ -85,11 +86,6 @@ module serv_csr
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mcause31 <= i_mtip & o_timer_irq_en;
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mcause3_0 <= (i_mtip & o_timer_irq_en) ? 4'd7 : i_mcause[3:0];
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end
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if (i_mscratch_en)
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mscratch <= {csr_in, mscratch[31:1]};
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if (i_mtvec_en)
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mtvec <= {csr_in, mtvec[31:1]};
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if (i_mepc_en | i_trap)
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mepc <= {i_trap ? i_pc : csr_in, mepc[31:1]};
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173
rtl/serv_mpram.v
Normal file
173
rtl/serv_mpram.v
Normal file
@ -0,0 +1,173 @@
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`default_nettype none
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module serv_mpram
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(
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input wire i_clk,
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input wire i_rst,
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//MEPC write port
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input wire i_mepc_wen,
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input wire i_mepc,
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//MTVAL write port
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input wire i_mtval_wen,
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input wire i_mtval,
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//CSR interface
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input wire i_csr_mscratch_en,
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input wire i_csr_mtvec_en,
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input wire i_csr,
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output wire o_csr,
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//RD write port
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input wire i_rd_wen,
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input wire [4:0] i_rd_waddr,
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input wire i_rd,
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input wire i_rreq,
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output reg o_rgnt,
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//RS1 read port
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input wire [4:0] i_rs1_raddr,
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output wire o_rs1,
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//RS2 read port
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input wire [4:0] i_rs2_raddr,
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output wire o_rs2);
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reg [1:0] csr_addr;
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wire csr_en = i_csr_mscratch_en|i_csr_mtvec_en;
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wire [8:0] waddr;
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reg [4:0] wdata0;
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reg [5:0] wdata1;
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reg [6:0] wdata2;
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reg [7:0] wdata3;
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wire [3:0] wdata;
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wire wen;
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reg [3:0] wen_r;
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reg [3:0] wcnt_lo;
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reg [2:0] wcnt_hi;
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assign wdata = wcnt_lo[0] ? wdata0[3:0] :
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wcnt_lo[1] ? wdata1[3:0] :
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wcnt_lo[2] ? wdata2[3:0] :
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/*wcnt_lo[3] ?*/ wdata3[3:0];
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assign wen = !wgo_r & |(wen_r & wcnt_lo);
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reg [4:0] rd_waddr;
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//mepc 100000
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//mtval 100011
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//csr 1000xx
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//rd 0xxxxx
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assign waddr[8] = !wcnt_lo[3];
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assign waddr[7:5] = wcnt_lo[3] ? rd_waddr[4:2] : 3'b000;
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assign waddr[4:3] = wcnt_lo[3] ? rd_waddr[1:0] :
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wcnt_lo[2] ? csr_addr :
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wcnt_lo[1] ? 2'b11 : 2'b00;
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assign waddr[2:0] = wcnt_hi;
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wire wgo = !(|wcnt_lo) & |({i_rd_wen,csr_en,i_mtval_wen,i_mepc_wen});
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reg wgo_r;
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always @(posedge i_clk) begin
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if (wgo) begin
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wgo_r <= 1'b1;
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wen_r <= {i_rd_wen,csr_en,i_mtval_wen,i_mepc_wen};
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rd_waddr <= i_rd_waddr;
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end
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wdata0 <= {i_mepc,wdata0[4:1]};
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wdata1 <= {i_mtval,wdata1[5:1]};
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wdata2 <= {i_csr,wdata2[6:1]};
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wdata3 <= {i_rd,wdata3[7:1]};
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wcnt_lo <= {wcnt_lo[2:0],wcnt_lo[3] | wgo};
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if (wcnt_lo[3]) begin
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wcnt_hi <= wcnt_hi + 1;
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if (wcnt_hi == 3'd7) begin
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wgo_r <= !wgo_r;
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wcnt_lo[0] <= wgo_r;
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wcnt_hi <= wcnt_hi + {2'b00,wgo_r};
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end
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end
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if (i_rst) begin
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wgo_r <= 1'b0;
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wcnt_lo <= 4'd0;
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wcnt_hi <= 3'd7;
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end
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end
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//0 : RS1
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//1 : RS2
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//2 : CSR
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reg [2:0] rcnt_hi;
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reg [3:0] rcnt_lo;
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wire [8:0] raddr;
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reg [3:0] rdata;
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reg [5:0] rdata0;
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reg [4:0] rdata1;
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reg [3:0] rdata2;
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//reg [3:0] rdata3;
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reg [2:0] rreq;
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always @(posedge i_clk) begin
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{o_rgnt,rreq} <= {rreq[2:0],i_rreq};
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if (rcnt_lo[3])
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rcnt_hi <= rcnt_hi + 1;
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if (i_rreq) begin
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rcnt_lo <= 4'd1;
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rcnt_hi <= 3'd0;
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csr_addr <= {1'b0,i_csr_mtvec_en};
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end else
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rcnt_lo <= {rcnt_lo[2:0],rcnt_lo[3]};
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rdata0[4:0] <= rdata0[5:1];
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rdata1[3:0] <= rdata1[4:1];
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rdata2[2:0] <= rdata2[3:1];
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//rdata3[2:0] <= rdata3[3:1];
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if (rcnt_lo[1]) rdata0[5:2] <= rdata;
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if (rcnt_lo[2]) rdata1[4:1] <= rdata;
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if (rcnt_lo[3]) rdata2[3:0] <= rdata;
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//if (rcnt_lo[0]) rdata3[3:0] <= rdata;
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if (i_rst) begin
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o_rgnt <= 1'b0;
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rreq <= 3'd0;
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end
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end
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assign raddr[8] = rcnt_lo[2];
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assign raddr[7:5] = rcnt_lo[0] ? i_rs1_raddr[4:2] :
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rcnt_lo[1] ? i_rs2_raddr[4:2] : 3'd0;
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assign raddr[4:3] = rcnt_lo[0] ? i_rs1_raddr[1:0] :
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rcnt_lo[1] ? i_rs2_raddr[1:0] : csr_addr;
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assign raddr[2:0] = rcnt_hi;
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assign o_rs1 = rdata0[0];
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assign o_rs2 = rdata1[0];
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assign o_csr = rdata2[0] & csr_en;
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reg [3:0] memory [0:511];
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always @(posedge i_clk) begin
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if (wen)
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`ifdef RISCV_FORMAL
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if (!i_rst)
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`endif
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memory[waddr] <= wdata;
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rdata <= memory[raddr];
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end
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`ifdef RISCV_FORMAL
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integer i;
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initial
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for (i=0;i<256;i=i+1)
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memory[i] = 4'd0;
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`endif
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endmodule
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@ -277,7 +277,7 @@ module serv_top
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.o_sh_done (alu_sh_done),
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.i_rd_sel (alu_rd_sel),
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.o_rd (alu_rd));
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/*
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serv_regfile regfile
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(
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.i_clk (clk),
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@ -291,6 +291,39 @@ module serv_top
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.i_rs2_addr (rs2_addr),
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.o_rs1 (rs1),
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.o_rs2 (rs2));
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*/
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wire csr_in;
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wire rf_csr_out;
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serv_mpram regfile
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(
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.i_clk (clk),
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.i_rst (i_rst),
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//MEPC write port
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.i_mepc_wen (1'b0),
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.i_mepc (1'b0),
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//MTVAL write port
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.i_mtval_wen (1'b0),
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.i_mtval (1'b0),
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//CSR write port
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.i_csr_mscratch_en (csr_mscratch_en),
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.i_csr_mtvec_en (csr_mtvec_en),
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.i_csr (csr_in),
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//RD write port
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.i_rd_wen (rd_en & (|rd_addr)),
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.i_rd_waddr (rd_addr),
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.i_rd (rd),
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.i_rreq (i_ibus_ack),
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.o_rgnt (rf_ready),
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//RS1 read port
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.i_rs1_raddr (rs1_addr),
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.o_rs1 (rs1),
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//RS2 read port
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.i_rs2_raddr (rs2_addr),
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.o_rs2 (rs2),
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//CSR read port
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.o_csr (rf_csr_out));
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serv_mem_if mem_if
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(
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@ -319,13 +352,13 @@ module serv_top
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.i_clk (clk),
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.i_cnt (cnt),
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.i_cnt_r (cnt_r),
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.i_rf_csr_out (rf_csr_out),
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.o_csr_in (csr_in),
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.i_mtip (i_timer_irq),
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.o_timer_irq_en ( timer_irq_en),
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.i_mstatus_en (csr_mstatus_en),
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.i_mie_en (csr_mie_en ),
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.i_mtvec_en (csr_mtvec_en ),
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.i_mip_en (csr_mip_en ),
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.i_mscratch_en (csr_mscratch_en),
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.i_mepc_en (csr_mepc_en ),
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.i_mcause_en (csr_mcause_en ),
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.i_mtval_en (csr_mtval_en ),
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