Olof Kindgren 66000a77f5 beq, sw

2018-10-28 23:54:04 +01:00

bench

jal, addi, lui, lb

2018-10-26 22:52:39 +02:00

data

jal, addi, lui, lb

2018-10-26 22:52:39 +02:00

firmware

Initial commit

2018-10-23 23:45:41 +02:00

rtl

beq, sw

2018-10-28 23:54:04 +01:00

barrel.mem

Initial commit

2018-10-23 23:45:41 +02:00

decode.mem

Initial commit

2018-10-23 23:45:41 +02:00

firmware.hex

Initial commit

2018-10-23 23:45:41 +02:00

ser_add_tb.v

Initial commit

2018-10-23 23:45:41 +02:00

serv_top_tb.v

Initial commit

2018-10-23 23:45:41 +02:00

serv.core

beq, sw

2018-10-28 23:54:04 +01:00

Description

SERV - The SErial RISC-V CPU

20 MiB

Languages

Verilog 81.2%

C 8%

C++ 2.9%

Assembly 2.2%

Tcl 1.7%

Other 4%