mirror of
https://github.com/olofk/serv.git
synced 2026-05-02 22:42:41 +00:00
16 lines
201 B
Verilog
16 lines
201 B
Verilog
module ser_eq
|
|
(
|
|
input clk,
|
|
input a,
|
|
input b,
|
|
input clr,
|
|
output q);
|
|
|
|
reg eq = 1'b1;
|
|
|
|
assign q = eq & (a == b);
|
|
always @(posedge clk)
|
|
eq <= q | clr;
|
|
|
|
endmodule
|