Olof Kindgren 7666ac4092 synthesized netlist works

2018-11-18 13:05:38 +01:00

..

camd_ram.v

jal, addi, lui, lb

2018-10-26 22:52:39 +02:00

riscv_timer.v

Add explicit wire defs to ports

2018-11-17 21:30:03 +01:00

ser_add.v

Add explicit wire defs to ports

2018-11-17 21:30:03 +01:00

ser_eq.v

Add explicit wire defs to ports

2018-11-17 21:30:03 +01:00

ser_lt.v

Add explicit wire defs to ports

2018-11-17 21:30:03 +01:00

ser_shift.v

Add explicit wire defs to ports

2018-11-17 21:30:03 +01:00

serv_alu.v

Add explicit wire defs to ports

2018-11-17 21:30:03 +01:00

serv_csr.v

Add explicit wire defs to ports

2018-11-17 21:30:03 +01:00

serv_ctrl.v

synthesized netlist works

2018-11-18 13:05:38 +01:00

serv_decode.v

synthesized netlist works

2018-11-18 13:05:38 +01:00

serv_mem_if.v

Add explicit wire defs to ports

2018-11-17 21:30:03 +01:00

serv_params.vh

Pass compliance tests

2018-11-15 14:16:01 +01:00

serv_regfile.v

Add explicit wire defs to ports

2018-11-17 21:30:03 +01:00

serv_top.v

synthesized netlist works

2018-11-18 13:05:38 +01:00

shift_reg.v

Add explicit wire defs to ports

2018-11-17 21:30:03 +01:00

wb_gpio.v

synthesized netlist works

2018-11-18 13:05:38 +01:00