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21 lines
423 B
Verilog
21 lines
423 B
Verilog
`default_nettype none
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module testhalt
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(
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input i_wb_clk,
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input [31:0] i_wb_dat,
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input i_wb_we,
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input i_wb_cyc,
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input i_wb_stb,
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output reg o_wb_ack = 1'b0);
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always @(posedge i_wb_clk) begin
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if (i_wb_cyc & i_wb_stb) begin
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$display("Test complete");
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$finish;
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end
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if (i_wb_cyc & i_wb_stb & !o_wb_ack)
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o_wb_ack <= 1'b1;
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end
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endmodule
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