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12 Commits 11 Branches 9 Tags
a92c933af1500f0f8a71033478890afe8f19e3be
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Olof Kindgren a92c933af1 csr, verilator, traps
2018-11-14 12:16:20 +01:00
bench
csr, verilator, traps
2018-11-14 12:16:20 +01:00
data
jal, addi, lui, lb
2018-10-26 22:52:39 +02:00
picorv32_firmware
Update firmware
2018-11-09 21:28:40 +01:00
rtl
csr, verilator, traps
2018-11-14 12:16:20 +01:00
barrel.mem
Initial commit
2018-10-23 23:45:41 +02:00
decode.mem
Initial commit
2018-10-23 23:45:41 +02:00
firmware.hex
Update firmware
2018-11-09 21:28:40 +01:00
ser_add_tb.v
Initial commit
2018-10-23 23:45:41 +02:00
serv_top_tb.v
Initial commit
2018-10-23 23:45:41 +02:00
serv.core
csr, verilator, traps
2018-11-14 12:16:20 +01:00
testhalt.v
csr, verilator, traps
2018-11-14 12:16:20 +01:00
testprint.v
csr, verilator, traps
2018-11-14 12:16:20 +01:00
Description
SERV - The SErial RISC-V CPU
20 MiB
Languages
Verilog 81.2%
C 8%
C++ 2.9%
Assembly 2.2%
Tcl 1.7%
Other 4%