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42 lines
961 B
Verilog
42 lines
961 B
Verilog
module serv_bufreg
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(
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input wire i_clk,
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input wire i_cnt0,
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input wire i_cnt1,
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input wire i_en,
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input wire i_init,
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input wire i_rs1,
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input wire i_rs1_en,
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input wire i_imm,
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input wire i_imm_en,
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input wire i_clr_lsb,
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output reg [1:0] o_lsb,
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output wire [31:0] o_dbus_adr,
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output wire o_q);
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wire c, q;
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reg c_r;
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reg [31:0] data;
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wire clr_lsb = i_cnt0 & i_clr_lsb;
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assign {c,q} = {1'b0,(i_rs1 & i_rs1_en)} + {1'b0,(i_imm & i_imm_en & !clr_lsb)} + c_r;
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always @(posedge i_clk) begin
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//Make sure carry is cleared before loading new data
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c_r <= c & i_en;
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if (i_en)
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data <= {i_init ? q : o_q, data[31:1]};
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if (i_cnt0 & i_init)
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o_lsb[0] <= q;
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if (i_cnt1 & i_init)
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o_lsb[1] <= q;
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end
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assign o_q = data[0];
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assign o_dbus_adr = {data[31:2], 2'b00};
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endmodule
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