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Code Issues Releases Wiki Activity

Remove redundant bufreg_loop control signal

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Olof Kindgren 2020-12-22 22:04:53 +01:00
parent c9f41b54e8
commit a960fd768b
4 changed files with 1 additions and 10 deletions
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doc/serv_bufreg_int.png
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3
rtl/serv_bufreg.v
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@ -5,7 +5,6 @@ module serv_bufreg
input wire i_cnt1,
input wire i_en,
input wire i_init,
input wire i_loop,
input wire i_rs1,
input wire i_rs1_en,
input wire i_imm,
@ -28,7 +27,7 @@ module serv_bufreg
c_r <= c & i_en;
if (i_en)
data <= {(i_loop & !i_init) ? o_q : q, data[31:1]};
data <= {i_init ? q : o_q, data[31:1]};
if (i_cnt0 & i_init)
o_lsb[0] <= q;

5
rtl/serv_decode.v
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@ -16,7 +16,6 @@ module serv_decode
output wire o_slt_op,
output wire o_rd_op,
//To bufreg
output wire o_bufreg_loop,
output wire o_bufreg_rs1_en,
output wire o_bufreg_imm_en,
output wire o_bufreg_clr_lsb,
@ -77,10 +76,6 @@ module serv_decode
assign o_bufreg_rs1_en = !opcode[4] | (!opcode[1] & opcode[0]);
assign o_bufreg_imm_en = !opcode[2];
//Loop bufreg contents for shift operations
assign o_bufreg_loop = op_or_opimm;
//Clear LSB of immediate for BRANCH and JAL ops
//True for BRANCH and JAL
//False for JALR/LOAD/STORE/OP/OPIMM?

3
rtl/serv_top.v
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@ -105,7 +105,6 @@ module serv_top
wire bufreg_en;
wire bufreg_rs1_en;
wire bufreg_imm_en;
wire bufreg_loop;
wire bufreg_clr_lsb;
wire bufreg_q;
@ -222,7 +221,6 @@ module serv_top
.o_slt_op (slt_op),
.o_rd_op (rd_op),
//To bufreg
.o_bufreg_loop (bufreg_loop),
.o_bufreg_rs1_en (bufreg_rs1_en),
.o_bufreg_imm_en (bufreg_imm_en),
.o_bufreg_clr_lsb (bufreg_clr_lsb),
@ -285,7 +283,6 @@ module serv_top
.i_init (init),
.o_lsb (lsb),
//Control
.i_loop (bufreg_loop),
.i_rs1_en (bufreg_rs1_en),
.i_imm_en (bufreg_imm_en),
.i_clr_lsb (bufreg_clr_lsb),