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19 lines
263 B
Verilog
19 lines
263 B
Verilog
module ser_add
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(
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input clk,
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input a,
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input b,
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input clr,
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output q,
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output o_v);
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assign o_v = (a&b | a&c_r | b&c_r);
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reg c_r = 1'b0;
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assign q = a ^ b ^ c_r;
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always @(posedge clk)
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c_r <= !clr & o_v;
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endmodule
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