Olof Kindgren 836a013462 Fix clock generation

2018-12-06 22:12:03 +01:00

..

serv_arbiter.v

Synthesis fixes

2018-11-22 20:58:45 +01:00

serv_mux.v

Synthesis fixes

2018-11-22 20:58:45 +01:00

serv_soc_tb.cpp

Fix clock generation

2018-12-06 22:12:03 +01:00

serv_top_tb.v

synthesized netlist works

2018-11-18 13:05:38 +01:00

serv_wrapper.v

Add icepll generator and run tinyfpga BX at 32MHz

2018-12-03 12:26:17 +01:00