Olof Kindgren fc82862e96 Add icepll generator and run tinyfpga BX at 32MHz

2018-12-03 12:26:17 +01:00

..

riscv_timer.v

Interrupts working. Adding philosophers example

2018-11-26 23:03:40 +01:00

ser_add.v

Use custom interconnect. Runs on hw

2018-11-21 13:15:33 +01:00

ser_eq.v

Add explicit wire defs to ports

2018-11-17 21:30:03 +01:00

ser_lt.v

Add explicit wire defs to ports

2018-11-17 21:30:03 +01:00

ser_shift.v

Add explicit wire defs to ports

2018-11-17 21:30:03 +01:00

serv_alu.v

Synthesis fixes

2018-11-22 20:58:45 +01:00

serv_clock_gen.v

Add icepll generator and run tinyfpga BX at 32MHz

2018-12-03 12:26:17 +01:00

serv_csr.v

Interrupts working. Adding philosophers example

2018-11-26 23:03:40 +01:00

serv_ctrl.v

Further optimizations

2018-11-23 21:26:49 +01:00

serv_decode.v

Interrupts working. Adding philosophers example

2018-11-26 23:03:40 +01:00

serv_mem_if.v

Further optimizations

2018-11-23 21:26:49 +01:00

serv_params.vh

First attempt att interrupt support

2018-11-26 16:01:07 +01:00

serv_regfile.v

Rewrite register file

2018-11-26 00:09:52 +01:00

serv_top.v

Interrupts working. Adding philosophers example

2018-11-26 23:03:40 +01:00

shift_reg.v

Synthesis fixes

2018-11-22 20:58:45 +01:00

wb_gpio.v

Use custom interconnect. Runs on hw

2018-11-21 13:15:33 +01:00