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https://github.com/olofk/serv.git
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127 lines
3.0 KiB
Verilog
127 lines
3.0 KiB
Verilog
`default_nettype none
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module serv_rf_if
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#(parameter WITH_CSR = 1)
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(//RF Interface
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output wire [4+WITH_CSR:0] o_wreg0,
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output wire [4+WITH_CSR:0] o_wreg1,
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output wire o_wen0,
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output wire o_wen1,
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output wire o_wdata0,
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output wire o_wdata1,
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output wire [4+WITH_CSR:0] o_rreg0,
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output wire [4+WITH_CSR:0] o_rreg1,
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input wire i_rdata0,
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input wire i_rdata1,
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//Trap interface
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input wire i_trap,
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input wire i_mret,
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input wire i_mepc,
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input wire i_mem_misalign,
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input wire i_bufreg_q,
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input wire i_bad_pc,
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output wire o_csr_pc,
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//CSR interface
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input wire i_csr_en,
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input wire [1:0] i_csr_addr,
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input wire i_csr,
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output wire o_csr,
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//RD write port
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input wire i_rd_wen,
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input wire [4:0] i_rd_waddr,
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input wire i_ctrl_rd,
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input wire i_alu_rd,
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input wire i_rd_alu_en,
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input wire i_csr_rd,
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input wire i_rd_csr_en,
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input wire i_mem_rd,
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//RS1 read port
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input wire [4:0] i_rs1_raddr,
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output wire o_rs1,
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//RS2 read port
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input wire [4:0] i_rs2_raddr,
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output wire o_rs2);
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`include "serv_params.vh"
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/*
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********** Write side ***********
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*/
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wire rd_wen = i_rd_wen & (|i_rd_waddr);
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generate
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if (WITH_CSR) begin
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wire rd = (i_ctrl_rd ) |
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(i_alu_rd & i_rd_alu_en) |
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(i_csr_rd & i_rd_csr_en) |
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(i_mem_rd);
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wire mtval = i_mem_misalign ? i_bufreg_q : i_bad_pc;
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assign o_wdata0 = i_trap ? mtval : rd;
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assign o_wdata1 = i_trap ? i_mepc : i_csr;
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//port 0 rd mtval
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//port 1 csr mepc
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//mepc 100010
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//mtval 100011
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//csr 1000xx
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//rd 0xxxxx
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assign o_wreg0 = i_trap ? {4'b1000,CSR_MTVAL} : {1'b0,i_rd_waddr};
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assign o_wreg1 = i_trap ? {4'b1000,CSR_MEPC} : {4'b1000,i_csr_addr};
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assign o_wen0 = i_trap | rd_wen;
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assign o_wen1 = i_trap | i_csr_en;
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/*
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********** Read side ***********
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*/
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//0 : RS1
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//1 : RS2 / CSR
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assign o_rreg0 = {1'b0, i_rs1_raddr};
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assign o_rreg1 =
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i_trap ? {4'b1000, CSR_MTVEC} :
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i_mret ? {4'b1000, CSR_MEPC} :
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i_csr_en ? {4'b1000, i_csr_addr} :
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{1'b0,i_rs2_raddr};
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assign o_rs1 = i_rdata0;
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assign o_rs2 = i_rdata1;
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assign o_csr = i_rdata1 & i_csr_en;
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assign o_csr_pc = i_rdata1;
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end else begin
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wire rd = (i_ctrl_rd ) |
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(i_alu_rd & i_rd_alu_en) |
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(i_mem_rd);
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assign o_wdata0 = rd;
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assign o_wdata1 = 1'b0;
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assign o_wreg0 = i_rd_waddr;
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assign o_wreg1 = 5'd0;
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assign o_wen0 = rd_wen;
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assign o_wen1 = 1'b0;
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/*
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********** Read side ***********
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*/
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assign o_rreg0 = i_rs1_raddr;
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assign o_rreg1 = i_rs2_raddr;
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assign o_rs1 = i_rdata0;
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assign o_rs2 = i_rdata1;
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assign o_csr = 1'b0;
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assign o_csr_pc = 1'b0;
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end // else: !if(WITH_CSR)
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endgenerate
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endmodule
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