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TIMER: Fix threshold for short vs long interval delay scheduling

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This commit is contained in:
Mark Pizzolato 2017-06-13 08:18:10 -07:00
parent d9e7afc92f
commit 17cc00f33e
1 changed files with 1 additions and 1 deletions
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2
sim_timer.c
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@ -2376,7 +2376,7 @@ if ((sim_calb_tmr != -1) && (rtc_hz[sim_calb_tmr])) { /* Calibrated Timer
uint32 usecs_til_calib = (uint32)ceil(inst_til_calib / inst_per_usec);
if (uptr != &sim_timer_units[sim_calb_tmr]) { /* Not scheduling calibrated timer? */
if (inst_delay_d >= (double)inst_til_calib) { /* long wait? */
if (inst_delay_d > (double)inst_til_calib) { /* long wait? */
stat = sim_clock_coschedule_tmr (uptr, sim_calb_tmr, ticks_til_calib - 1);
uptr->usecs_remaining = (stat == SCPE_OK) ? usec_delay - usecs_til_calib : 0.0;
sim_debug (DBG_TIM, &sim_timer_dev, "sim_timer_activate_after(%s, %.0f usecs) - coscheduling with with calibrated timer(%d), ticks=%d, usecs_remaining=%.0f usecs, inst_til_tick=%d\n",