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VAX, VAX780: Added model-specific AST validation test

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From page 6-6 of DEC STD 032 (the VAX architecture spec):
"Execution of MTPR src, #PR$_ASTLVL with src<31:0> GEQU 5 results in
UNDEFINED behavior. The preferred implementation is to cause a reserved
operand fault." MicroVAX II, CVAX, and Rigel all conform to the preferred
behavior, as does the current simulator, which was written from the CVAX
microcode. NVAX masks to 3b and does not take an exception on a value
GEQU 5.

The 1982 Architecture Handbook describes ASTLVL as a 3b register, with
src<31:3> ignored/read as zero, and exceptions taken on values GEQU 5.
The780 microcode masks the input value to 3b before doing the GEQU 5 test.

The ASTLVL test needs to be model specific.

I suspect the behavior became undefined when MicroVAX II simplified the
original test to save a microword. I do not see how the code fragment Matt
references could work on a MicroVAX II, which was supported under 4.5.
Perhaps the device Matt mentions couldn't exist on a MicroVAX II?

For those who wants the gory details... uVAX, CVAX, and Rigel do an
unsigned compare on the unmasked src and the constant 5. Carry out
means reserved operand. Overflow is ignored. So an input of 0x80000002 -
0x00000005 (done in the data path as 0x80000002 + 0xFFFFFFFB) generates overflow (ignored) and carry out.
This commit is contained in:
Bob Supnik 2017-05-18 12:23:56 -07:00 committed by Mark Pizzolato
parent f6023f7039
commit 4d52ce023b
3 changed files with 11 additions and 4 deletions
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4
VAX/vax780_defs.h
View File

@ -23,6 +23,7 @@
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
18-May-17 RMS Added model-specific AST validation test
19-Jan-17 RMS Moved CR to BR6 (Mark Pizzolato)
29-Mar-15 RMS Added model specific IPR max
16-Dec-14 RMS Removed TQ boot code (780 VMB doesn't support tape boot)
@ -148,6 +149,9 @@
#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT
#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT
#define MT_AST_TEST(r) r = (r) & 07; \
if ((r) > AST_MAX) RSVD_OPND_FAULT
/* Memory */
#define MAXMEMWIDTH 23 /* max mem, MS780C */

3
VAX/vax_cpu1.c
View File

@ -1526,8 +1526,7 @@ switch (prn) { /* case on reg # */
break;
case MT_ASTLVL: /* ASTLVL */
if (val > AST_MAX) /* > 4? fault */
RSVD_OPND_FAULT;
MT_AST_TEST (val); /* trim, test val */
ASTLVL = val;
break;

8
VAX/vaxmod_defs.h
View File

@ -1,6 +1,6 @@
/* vaxmod_defs.h: VAX model-specific definitions file
Copyright (c) 1998-2015, Robert M Supnik
Copyright (c) 1998-2017, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -23,6 +23,7 @@
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
18-May-17 RMS Added model-specific AST validation test
29-Mar-15 RMS Added model-specific IPR max
20-Dec-13 RMS Added prototypes for unaligned IO and register handling
12-Dec-12 RMS Fixed IO base address for RQB, RQC, RQD
@ -207,7 +208,7 @@
#define CQMAMASK (CQMSIZE - 1) /* Qmem addr mask */
#define CQMBASE 0x30000000 /* Qmem base */
/* Machine specific reserved operand tests (all NOPs) */
/* Machine specific reserved operand tests (mostly NOPs) */
#define ML_PA_TEST(r)
#define ML_LR_TEST(r)
@ -217,6 +218,9 @@
#define LP_MBZ84_TEST(r)
#define LP_MBZ92_TEST(r)
#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT
/* Qbus I/O modes */
#define READ 0 /* PDP-11 compatibility */