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https://github.com/open-simh/simh.git
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PDP11: Add initial UC15 support from Bob Supnik
This commit is contained in:
Mark Pizzolato
parent
fa1fba5bd5
commit
99bbc5f8cf
@ -25,6 +25,9 @@
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cpu PDP-11 CPU
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04-Dec-16 RMS Removed duplicate IDLE entries in MTAB
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30-Aug-16 RMS Fixed overloading of -d in ex/mod
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14-Mar-16 RMS Added UC15 support
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06-Mar-16 RMS Fixed bug in history virtual addressing
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30-Dec-15 RMS Added NOBEVENT option for 11/03, 11/23
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29-Dec-15 RMS Call build_dib_tab during reset (Mark Pizzolato)
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@ -294,9 +297,9 @@ int32 stop_vecabort = 1; /* stop on vec abort */
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int32 stop_spabort = 1; /* stop on SP abort */
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int32 wait_enable = 0; /* wait state enable */
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int32 autcon_enb = 1; /* autoconfig enable */
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uint32 cpu_model = MOD_1173; /* CPU model */
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uint32 cpu_type = 1u << MOD_1173; /* model as bit mask */
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uint32 cpu_opt = SOP_1173; /* CPU options */
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uint32 cpu_model = INIMODEL; /* CPU model */
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uint32 cpu_type = 1u << INIMODEL; /* model as bit mask */
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uint32 cpu_opt = INIOPTNS; /* CPU options */
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uint16 pcq[PCQ_SIZE] = { 0 }; /* PC queue */
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int32 pcq_p = 0; /* PC queue ptr */
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REG *pcq_r = NULL; /* PC queue reg ptr */
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@ -305,7 +308,6 @@ int32 hst_p = 0; /* history pointer */
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int32 hst_lnt = 0; /* history length */
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InstHistory *hst = NULL; /* instruction history */
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int32 dsmask[4] = { MMR3_KDS, MMR3_SDS, 0, MMR3_UDS }; /* dspace enables */
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t_addr cpu_memsize = INIMEMSIZE; /* last mem addr */
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extern int32 CPUERR, MAINT;
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extern CPUTAB cpu_tab[];
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@ -556,6 +558,7 @@ REG cpu_reg[] = {
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MTAB cpu_mod[] = {
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{ MTAB_XTD|MTAB_VDV, 0, "TYPE", NULL,
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NULL, &cpu_show_model },
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#if !defined (UC15)
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{ MTAB_XTD|MTAB_VDV, MOD_1103, NULL, "11/03", &cpu_set_model },
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{ MTAB_XTD|MTAB_VDV, MOD_1104, NULL, "11/04", &cpu_set_model },
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{ MTAB_XTD|MTAB_VDV, MOD_1105, NULL, "11/05", &cpu_set_model },
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@ -592,8 +595,6 @@ MTAB cpu_mod[] = {
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{ MTAB_XTD|MTAB_VDV, OPT_MMU, NULL, "NOMMU", &cpu_clr_opt },
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{ MTAB_XTD|MTAB_VDV, OPT_BVT, NULL, "BEVENT", &cpu_set_opt },
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{ MTAB_XTD|MTAB_VDV, OPT_BVT, NULL, "NOBEVENT", &cpu_clr_opt },
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{ MTAB_XTD|MTAB_VDV, 0, "IDLE", "IDLE", &sim_set_idle, &sim_show_idle },
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{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOIDLE", &sim_clr_idle, NULL },
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{ UNIT_MSIZE, 16384, NULL, "16K", &cpu_set_size},
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{ UNIT_MSIZE, 32768, NULL, "32K", &cpu_set_size},
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{ UNIT_MSIZE, 49152, NULL, "48K", &cpu_set_size},
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@ -614,12 +615,22 @@ MTAB cpu_mod[] = {
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{ UNIT_MSIZE, 2097152, NULL, "2M", &cpu_set_size},
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{ UNIT_MSIZE, 3145728, NULL, "3M", &cpu_set_size},
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{ UNIT_MSIZE, 4186112, NULL, "4M", &cpu_set_size},
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "IOSPACE", NULL,
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NULL, &show_iospace },
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{ MTAB_XTD|MTAB_VDV, 1, "AUTOCONFIG", "AUTOCONFIG",
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&set_autocon, &show_autocon },
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{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOAUTOCONFIG",
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&set_autocon, NULL },
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#else
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{ MTAB_XTD|MTAB_VDV, MOD_1104, NULL, "11/04", &cpu_set_model },
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{ MTAB_XTD|MTAB_VDV, MOD_1105, NULL, "11/05", &cpu_set_model },
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{ MTAB_XTD|MTAB_VDV, MOD_1120, NULL, "11/20", &cpu_set_model },
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{ UNIT_MSIZE, 16384, NULL, "16K", &cpu_set_size},
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{ UNIT_MSIZE, 24576, NULL, "24K", &cpu_set_size},
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{ UNIT_MSIZE, 32768, NULL, "32K", &cpu_set_size},
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#endif
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "IOSPACE", NULL,
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NULL, &show_iospace },
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{ MTAB_XTD|MTAB_VDV, 0, "IDLE", "IDLE", &sim_set_idle, &sim_show_idle },
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{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOIDLE", &sim_clr_idle, NULL },
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "HISTORY", "HISTORY",
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&cpu_set_hist, &cpu_show_hist },
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "VIRTUAL", NULL,
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@ -654,9 +665,8 @@ t_stat reason;
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reason = build_dib_tab (); /* build, chk dib_tab */
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if (reason != SCPE_OK)
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return reason;
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if (MEMSIZE < cpu_tab[cpu_model].maxm) /* mem size < max? */
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cpu_memsize = MEMSIZE; /* then okay */
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else cpu_memsize = cpu_tab[cpu_model].maxm - IOPAGESIZE;/* max - io page */
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if (MEMSIZE >= (cpu_tab[cpu_model].maxm - IOPAGESIZE)) /* mem size >= max - io page? */
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MEMSIZE = cpu_tab[cpu_model].maxm - IOPAGESIZE; /* max - io page */
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cpu_type = 1u << cpu_model; /* reset type mask */
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cpu_bme = (MMR3 & MMR3_BME) && (cpu_opt & OPT_UBM); /* map enabled? */
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PC = saved_PC;
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@ -2291,7 +2301,7 @@ if ((va & 1) && CPUT (HAS_ODD)) { /* odd address? */
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}
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pa = relocR (va); /* relocate */
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if (ADDR_IS_MEM (pa)) /* memory address? */
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return (M[pa >> 1]);
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return RdMemW (pa);
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if ((pa < IOPAGEBASE) || /* not I/O address */
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(CPUT (CPUT_J) && (pa >= IOBA_CPU))) { /* or J11 int reg? */
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setCPUERR (CPUE_NXM);
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@ -2314,7 +2324,7 @@ if ((va & 1) && CPUT (HAS_ODD)) { /* odd address? */
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}
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pa = relocR (va); /* relocate */
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if (ADDR_IS_MEM (pa)) /* memory address? */
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return (M[pa >> 1]);
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return RdMemW (pa);
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if (pa < IOPAGEBASE) { /* not I/O address? */
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setCPUERR (CPUE_NXM);
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ABORT (TRAP_NXM);
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@ -2331,8 +2341,8 @@ int32 ReadB (int32 va)
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int32 pa, data;
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pa = relocR (va); /* relocate */
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if (ADDR_IS_MEM (pa))
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return (va & 1? M[pa >> 1] >> 8: M[pa >> 1]) & 0377;
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if (ADDR_IS_MEM (pa)) /* memory address? */
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return RdMemB (pa);
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if (pa < IOPAGEBASE) { /* not I/O address? */
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setCPUERR (CPUE_NXM);
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ABORT (TRAP_NXM);
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@ -2354,7 +2364,7 @@ if ((va & 1) && CPUT (HAS_ODD)) { /* odd address? */
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}
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last_pa = relocW (va); /* reloc, wrt chk */
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if (ADDR_IS_MEM (last_pa)) /* memory address? */
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return (M[last_pa >> 1]);
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return RdMemW (last_pa);
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if (last_pa < IOPAGEBASE) { /* not I/O address? */
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setCPUERR (CPUE_NXM);
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ABORT (TRAP_NXM);
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@ -2372,7 +2382,7 @@ int32 data;
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last_pa = relocW (va); /* reloc, wrt chk */
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if (ADDR_IS_MEM (last_pa))
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return (va & 1? M[last_pa >> 1] >> 8: M[last_pa >> 1]) & 0377;
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return RdMemB (last_pa);
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if (last_pa < IOPAGEBASE) { /* not I/O address? */
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setCPUERR (CPUE_NXM);
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ABORT (TRAP_NXM);
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@ -2403,7 +2413,7 @@ if ((va & 1) && CPUT (HAS_ODD)) { /* odd address? */
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}
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pa = relocW (va); /* relocate */
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if (ADDR_IS_MEM (pa)) { /* memory address? */
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M[pa >> 1] = data;
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WrMemW (pa, data);
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return;
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}
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if (pa < IOPAGEBASE) { /* not I/O address? */
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@ -2423,9 +2433,7 @@ int32 pa;
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pa = relocW (va); /* relocate */
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if (ADDR_IS_MEM (pa)) { /* memory address? */
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if (va & 1)
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M[pa >> 1] = (M[pa >> 1] & 0377) | (data << 8);
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else M[pa >> 1] = (M[pa >> 1] & ~0377) | data;
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WrMemB (pa, data);
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return;
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}
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if (pa < IOPAGEBASE) { /* not I/O address? */
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@ -2442,7 +2450,7 @@ return;
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void PWriteW (int32 data, int32 pa)
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{
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if (ADDR_IS_MEM (pa)) { /* memory address? */
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M[pa >> 1] = data;
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WrMemW (pa, data);
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return;
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}
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if (pa < IOPAGEBASE) { /* not I/O address? */
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@ -2459,9 +2467,7 @@ return;
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void PWriteB (int32 data, int32 pa)
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{
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if (ADDR_IS_MEM (pa)) { /* memory address? */
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if (pa & 1)
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M[pa >> 1] = (M[pa >> 1] & 0377) | (data << 8);
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else M[pa >> 1] = (M[pa >> 1] & ~0377) | data;
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WrMemB (pa, data);
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return;
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}
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if (pa < IOPAGEBASE) { /* not I/O address? */
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@ -3045,8 +3051,8 @@ if (sw & SWMASK ('V')) { /* -v */
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if (addr >= MAXMEMSIZE)
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return SCPE_REL;
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}
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if (addr < MEMSIZE) {
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*vptr = M[addr >> 1] & 0177777;
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if (ADDR_IS_MEM (addr)) {
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*vptr = RdMemW (addr) & 0177777;
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return SCPE_OK;
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}
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if (addr < IOPAGEBASE)
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@ -3067,8 +3073,8 @@ if (sw & SWMASK ('V')) { /* -v */
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if (addr >= MAXMEMSIZE)
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return SCPE_REL;
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}
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if (addr < MEMSIZE) {
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M[addr >> 1] = val & 0177777;
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if (ADDR_IS_MEM (addr)) {
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WrMemW (addr, val & 0177777);
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return SCPE_OK;
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}
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if (addr < IOPAGEBASE)
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@ -1,6 +1,6 @@
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/* pdp11_cpumod.c: PDP-11 CPU model-specific features
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Copyright (c) 2004-2013, Robert M Supnik
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Copyright (c) 2004-2016, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@ -25,6 +25,8 @@
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system PDP-11 model-specific registers
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04-Mar-16 RMS Fixed maximum memory sizes to exclude IO page
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14-Mar-16 RMS Modified to keep cpu_memsize in sync with MEMSIZE
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06-Jun-13 RMS Fixed change model to set memory size last
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20-May-08 RMS Added JCSR default for KDJ11B, KDJ11E
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22-Apr-08 RMS Fixed write behavior of 11/70 MBRK, LOSIZE, HISIZE
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@ -1149,9 +1151,11 @@ uint32 i, clim;
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uint16 *nM;
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if ((val <= 0) ||
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(val > (int32) cpu_tab[cpu_model].maxm) ||
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(val > ((int32) cpu_tab[cpu_model].maxm)) ||
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((val & 07777) != 0))
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return SCPE_ARG;
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if (val > ((int32) (cpu_tab[cpu_model].maxm - IOPAGESIZE)))
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val = (int32) (cpu_tab[cpu_model].maxm - IOPAGESIZE);
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for (i = val; i < MEMSIZE; i = i + 2)
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mc = mc | M[i >> 1];
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if ((mc != 0) && !get_yn ("Really truncate memory [N]?", FALSE))
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@ -1,6 +1,6 @@
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/* pdp11_cr.c: CR/CM/CD-11/CD20 card reader simulator
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Copyright (c) 2005-2010, John A. Dundas III
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Copyright (c) 2005-2016, John A. Dundas III
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Portions derived from work by Douglas W. Jones, jones@cs.uiowa.edu
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Portions derived from work by Robert M Supnik
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@ -100,6 +100,7 @@
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ECOs (at least) for Data Buffer status and augmented image mode.
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Revision History:
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14-Mar-16 RMS Added UC15 support (CR11 only)
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30-Mar-15 RMS Backported from GitHub master; removed extended
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help and Qbus support
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23-Feb-13 JGP Added DEC version of the 026 codepage
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@ -223,10 +224,12 @@ extern int32 int_req[IPL_HLVL];
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#define DFLT_DIS (DEV_QBUS) /* CR11 is programmed I/O only, Qbus OK */
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#define DFLT_TYPE (UNIT_CR11) /* Default, but changable */
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#define DFLT_CPM 285
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#define CR11_ONLY (1)
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#if !defined (UC15)
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#define CD11_OK (1) /* only on real PDP-11 */
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#define CD20_OK (1)
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#define AIECO_OK (1) /* Augmented Image ECO optional */
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#define CR11_OK (1)
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#define CD11_OK (1)
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#endif
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#endif
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/* **** No VM_xxx macros should be referenced after this line **** */
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@ -1,6 +1,6 @@
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/* pdp11_defs.h: PDP-11 simulator definitions
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Copyright (c) 1993-2015, Robert M Supnik
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Copyright (c) 1993-2016, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@ -26,6 +26,7 @@
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The author gratefully acknowledges the help of Max Burnet, Megan Gentry,
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and John Wilson in resolving questions about the PDP-11
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10-Mar-16 RMS Added UC15 support
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30-Dec-15 RMS Added NOBVT option
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23-Oct-13 RMS Added cpu_set_boot prototype
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02-Sep-13 RMS Added third Massbus adapter and RS drive
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@ -97,7 +98,6 @@
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#define VASIZE 0200000 /* 2**16 */
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#define VAMASK (VASIZE - 1) /* 2**16 - 1 */
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#define MEMSIZE64K 0200000 /* 2**16 */
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#define INIMEMSIZE 001000000 /* 2**18 */
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#define UNIMEMSIZE 001000000 /* 2**18 */
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#define UNIMASK (UNIMEMSIZE - 1) /* 2**18 - 1 */
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#define IOPAGEBASE 017760000 /* 2**22 - 2**13 */
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@ -106,7 +106,6 @@
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#define MAXMEMSIZE 020000000 /* 2**22 */
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#define PAMASK (MAXMEMSIZE - 1) /* 2**22 - 1 */
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#define MEMSIZE (cpu_unit.capac)
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#define ADDR_IS_MEM(x) (((t_addr) (x)) < cpu_memsize) /* use only in sim! */
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#define DMASK 0177777
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/* CPU models */
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@ -535,6 +534,10 @@ typedef struct pdp_dib DIB;
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#define IOLN_RQD 004
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#define IOBA_VH (IOPAGEBASE + 000440) /* DHQ11 */
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#define IOLN_VH 020
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#define IOBA_UCA (IOPAGEBASE + 007770) /* UC15 DR11 #1 */
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#define IOLN_UCA 006
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#define IOBA_UCB (IOPAGEBASE + 007760) /* UC15 DR11 #2 */
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#define IOLN_UCB 006
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#define IOBA_UBM (IOPAGEBASE + 010200) /* Unibus map */
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#define IOLN_UBM (UBM_LNT_LW * sizeof (int32))
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#define IOBA_RS (IOPAGEBASE + 012040) /* RHC: RS03/RS04 */
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@ -644,6 +647,7 @@ typedef struct pdp_dib DIB;
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#define IPL_HMIN 4 /* lowest IO int level */
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#define INT_V_PIR7 0 /* BR7 */
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#define INT_V_UCA 1
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#define INT_V_PIR6 0 /* BR6 */
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#define INT_V_CLK 1
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@ -670,6 +674,7 @@ typedef struct pdp_dib DIB;
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#define INT_V_RF 16
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#define INT_V_RC 17
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#define INT_V_RS 18
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#define INT_V_UCB 19
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#define INT_V_PIR4 0 /* BR4 */
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#define INT_V_TTI 1
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@ -690,6 +695,7 @@ typedef struct pdp_dib DIB;
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#define INT_V_PIR1 0 /* BR1 */
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#define INT_PIR7 (1u << INT_V_PIR7)
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#define INT_UCB (1u << INT_V_UCB)
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#define INT_PIR6 (1u << INT_V_PIR6)
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#define INT_CLK (1u << INT_V_CLK)
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#define INT_PCLK (1u << INT_V_PCLK)
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@ -714,6 +720,7 @@ typedef struct pdp_dib DIB;
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#define INT_RF (1u << INT_V_RF)
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#define INT_RC (1u << INT_V_RC)
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#define INT_RS (1u << INT_V_RS)
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#define INT_UCA (1u << INT_V_UCA)
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#define INT_PIR4 (1u << INT_V_PIR4)
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#define INT_TTI (1u << INT_V_TTI)
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#define INT_TTO (1u << INT_V_TTO)
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@ -739,7 +746,8 @@ typedef struct pdp_dib DIB;
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#define INT_INTERNAL2 (INT_PIR2)
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#define INT_INTERNAL1 (INT_PIR1)
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#define IPL_CLK 6 /* int pri levels */
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#define IPL_UCB 7 /* int pri levels */
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#define IPL_CLK 6
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#define IPL_PCLK 6
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#define IPL_DTA 6
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#define IPL_TA 6
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@ -761,6 +769,7 @@ typedef struct pdp_dib DIB;
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#define IPL_RF 5
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#define IPL_RC 5
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#define IPL_RS 5
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#define IPL_UCA 5
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#define IPL_PTR 4
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#define IPL_PTP 4
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#define IPL_TTI 4
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@ -820,6 +829,8 @@ typedef struct pdp_dib DIB;
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#define VEC_DZTX 0304
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#define VEC_VHRX 0310
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#define VEC_VHTX 0314
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#define VEC_UCA 0300
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#define VEC_UCB 0310
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/* Interrupt macros */
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@ -872,4 +883,39 @@ void cpu_set_boot (int32 pc);
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|
||||
#include "pdp11_io_lib.h"
|
||||
|
||||
#if defined (UC15) /* UC15 */
|
||||
#define INIMODEL MOD_1105
|
||||
#define INIOPTNS SOP_1105
|
||||
#define INIMEMSIZE 00040000 /* 16KB */
|
||||
#define ADDR_IS_MEM(x) (((uint32) (x)) < uc15_memsize)
|
||||
|
||||
#define RdMemW(pa) uc15_RdMemW (pa)
|
||||
#define RdMemB(pa) uc15_RdMemB (pa)
|
||||
#define WrMemW(pa,d) uc15_WrMemW (pa, d)
|
||||
#define WrMemB(pa, d) uc15_WrMemB (pa, d)
|
||||
|
||||
uint32 uc15_memsize;
|
||||
int32 uc15_RdMemW (int32 pa);
|
||||
int32 uc15_RdMemB (int32 pa);
|
||||
void uc15_WrMemW (int32 pa, int32 d);
|
||||
void uc15_WrMemB (int32 pa, int32 d);
|
||||
int32 Map_Read18 (uint32 ba, int32 bc, uint32 *buf);
|
||||
int32 Map_Write18 (uint32 ba, int32 bc, uint32 *buf);
|
||||
|
||||
#else /* PDP-11 */
|
||||
|
||||
#define INIMODEL MOD_1173
|
||||
#define INIOPTNS SOP_1173
|
||||
#define INIMEMSIZE 001000000 /* 2**18 */
|
||||
#define ADDR_IS_MEM(x) (((t_addr) (x)) < MEMSIZE)
|
||||
|
||||
#define RdMemW(pa) (M[(pa) >> 1])
|
||||
#define RdMemB(pa) ((((pa) & 1)? M[(pa) >> 1] >> 8: M[(pa) >> 1]) & 0377)
|
||||
#define WrMemW(pa,d) M[(pa) >> 1] = (d)
|
||||
#define WrMemB(pa,d) M[(pa) >> 1] = ((pa) & 1)? \
|
||||
((M[(pa) >> 1] & 0377) | (((d) & 0377) << 8)): \
|
||||
((M[(pa) >> 1] & ~0377) | ((d) & 0377))
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@ -61,7 +61,7 @@ extern int32 cpu_log;
|
||||
extern int32 autcon_enb;
|
||||
extern int32 uba_last;
|
||||
extern DEVICE cpu_dev;
|
||||
extern t_addr cpu_memsize;
|
||||
extern UNIT cpu_unit;
|
||||
|
||||
int32 calc_ints (int32 nipl, int32 trq);
|
||||
|
||||
@ -250,9 +250,7 @@ if (cpu_bme) { /* map enabled? */
|
||||
ma = Map_Addr (ba); /* map addr */
|
||||
if (!ADDR_IS_MEM (ma)) /* NXM? err */
|
||||
return (lim - ba);
|
||||
if (ma & 1) /* get byte */
|
||||
*buf++ = (M[ma >> 1] >> 8) & 0377;
|
||||
else *buf++ = M[ma >> 1] & 0377;
|
||||
*buf++ = (uint8) RdMemB (ma); /* get byte */
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
@ -260,12 +258,10 @@ else { /* physical */
|
||||
if (ADDR_IS_MEM (lim)) /* end ok? */
|
||||
alim = lim;
|
||||
else if (ADDR_IS_MEM (ba)) /* no, strt ok? */
|
||||
alim = cpu_memsize;
|
||||
alim = MEMSIZE;
|
||||
else return bc; /* no, err */
|
||||
for ( ; ba < alim; ba++) { /* by bytes */
|
||||
if (ba & 1)
|
||||
*buf++ = (M[ba >> 1] >> 8) & 0377; /* get byte */
|
||||
else *buf++ = M[ba >> 1] & 0377;
|
||||
*buf++ = (uint8) RdMemB (ba); /* get byte */
|
||||
}
|
||||
return (lim - alim);
|
||||
}
|
||||
@ -282,7 +278,7 @@ if (cpu_bme) { /* map enabled? */
|
||||
ma = Map_Addr (ba); /* map addr */
|
||||
if (!ADDR_IS_MEM (ma)) /* NXM? err */
|
||||
return (lim - ba);
|
||||
*buf++ = M[ma >> 1];
|
||||
*buf++ = (uint16) RdMemW (ma);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
@ -290,10 +286,10 @@ else { /* physical */
|
||||
if (ADDR_IS_MEM (lim)) /* end ok? */
|
||||
alim = lim;
|
||||
else if (ADDR_IS_MEM (ba)) /* no, strt ok? */
|
||||
alim = cpu_memsize;
|
||||
alim = MEMSIZE;
|
||||
else return bc; /* no, err */
|
||||
for ( ; ba < alim; ba = ba + 2) { /* by words */
|
||||
*buf++ = M[ba >> 1];
|
||||
*buf++ = (uint16) RdMemW (ba);
|
||||
}
|
||||
return (lim - alim);
|
||||
}
|
||||
@ -310,9 +306,7 @@ if (cpu_bme) { /* map enabled? */
|
||||
ma = Map_Addr (ba); /* map addr */
|
||||
if (!ADDR_IS_MEM (ma)) /* NXM? err */
|
||||
return (lim - ba);
|
||||
if (ma & 1) M[ma >> 1] = (M[ma >> 1] & 0377) |
|
||||
((uint16) *buf++ << 8);
|
||||
else M[ma >> 1] = (M[ma >> 1] & ~0377) | *buf++;
|
||||
WrMemB (ma, ((uint16) *buf++));
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
@ -320,12 +314,10 @@ else { /* physical */
|
||||
if (ADDR_IS_MEM (lim)) /* end ok? */
|
||||
alim = lim;
|
||||
else if (ADDR_IS_MEM (ba)) /* no, strt ok? */
|
||||
alim = cpu_memsize;
|
||||
alim = MEMSIZE;
|
||||
else return bc; /* no, err */
|
||||
for ( ; ba < alim; ba++) { /* by bytes */
|
||||
if (ba & 1)
|
||||
M[ba >> 1] = (M[ba >> 1] & 0377) | ((uint16) *buf++ << 8);
|
||||
else M[ba >> 1] = (M[ba >> 1] & ~0377) | *buf++;
|
||||
WrMemB (ba, ((uint16) *buf++));
|
||||
}
|
||||
return (lim - alim);
|
||||
}
|
||||
@ -342,7 +334,7 @@ if (cpu_bme) { /* map enabled? */
|
||||
ma = Map_Addr (ba); /* map addr */
|
||||
if (!ADDR_IS_MEM (ma)) /* NXM? err */
|
||||
return (lim - ba);
|
||||
M[ma >> 1] = *buf++;
|
||||
WrMemW (ma, *buf++);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
@ -350,10 +342,10 @@ else { /* physical */
|
||||
if (ADDR_IS_MEM (lim)) /* end ok? */
|
||||
alim = lim;
|
||||
else if (ADDR_IS_MEM (ba)) /* no, strt ok? */
|
||||
alim = cpu_memsize;
|
||||
alim = MEMSIZE;
|
||||
else return bc; /* no, err */
|
||||
for ( ; ba < alim; ba = ba + 2) { /* by words */
|
||||
M[ba >> 1] = *buf++;
|
||||
WrMemW (ba, *buf++);
|
||||
}
|
||||
return (lim - alim);
|
||||
}
|
||||
|
||||
@ -164,7 +164,7 @@ extern uint32 cpu_opt;
|
||||
extern int32 cpu_bme;
|
||||
extern uint16 *M;
|
||||
extern int32 int_req[IPL_HLVL];
|
||||
extern t_addr cpu_memsize;
|
||||
extern UNIT cpu_unit;
|
||||
|
||||
t_stat mba_reset (DEVICE *dptr);
|
||||
t_stat mba_rd (int32 *val, int32 pa, int32 access);
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/* pdp11_rk.c: RK11/RKV11 cartridge disk simulator
|
||||
|
||||
Copyright (c) 1993-2013, Robert M Supnik
|
||||
Copyright (c) 1993-2016, Robert M Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
@ -25,6 +25,7 @@
|
||||
|
||||
rk RK11/RKV11/RK05 cartridge disk
|
||||
|
||||
12-Mar-16 RMS Revised to support UC15 (18b IO)
|
||||
23-Oct-13 RMS Revised for new boot setup routine
|
||||
06-Sep-13 RMS Fixed RKDS content for non-existent disk (Mark Pizzolato)
|
||||
20-Mar-09 RMS Fixed bug in read header (Walter F Mueller)
|
||||
@ -71,6 +72,22 @@
|
||||
|
||||
/* Constants */
|
||||
|
||||
#if defined (UC15)
|
||||
|
||||
#define RKCONTR uint32 /* container format */
|
||||
#define RKWRDSZ 18 /* word width */
|
||||
#define MAP_RDW(a,b,c) Map_Read18 (a, b, c)
|
||||
#define MAP_WRW(a,b,c) Map_Write18 (a, b, c)
|
||||
|
||||
#else
|
||||
|
||||
#define RKCONTR uint16
|
||||
#define RKWRDSZ 16
|
||||
#define MAP_RDW(a,b,c) Map_ReadW (a, b, c)
|
||||
#define MAP_WRW(a,b,c) Map_WriteW (a, b, c)
|
||||
|
||||
#endif
|
||||
|
||||
#define RK_NUMWD 256 /* words/sector */
|
||||
#define RK_NUMSC 12 /* sectors/surface */
|
||||
#define RK_NUMSF 2 /* surfaces/cylinder */
|
||||
@ -179,10 +196,9 @@
|
||||
#define RK_MIN 10
|
||||
#define MAX(x,y) (((x) > (y))? (x): (y))
|
||||
|
||||
extern uint16 *M; /* memory */
|
||||
extern int32 int_req[IPL_HLVL];
|
||||
|
||||
uint16 *rkxb = NULL; /* xfer buffer */
|
||||
RKCONTR *rkxb = NULL; /* xfer buffer */
|
||||
int32 rkcs = 0; /* control/status */
|
||||
int32 rkds = 0; /* drive status */
|
||||
int32 rkba = 0; /* memory address */
|
||||
@ -271,7 +287,7 @@ MTAB rk_mod[] = {
|
||||
|
||||
DEVICE rk_dev = {
|
||||
"RK", rk_unit, rk_reg, rk_mod,
|
||||
RK_NUMDR, 8, 24, 1, 8, 16,
|
||||
RK_NUMDR, 8, 24, 1, 8, RKWRDSZ,
|
||||
NULL, NULL, &rk_reset,
|
||||
&rk_boot, NULL, NULL,
|
||||
&rk_dib, DEV_DISABLE | DEV_UBUS | DEV_Q18
|
||||
@ -488,7 +504,7 @@ t_stat rk_svc (UNIT *uptr)
|
||||
int32 i, drv, err, awc, wc, cma, cda, t;
|
||||
int32 da, cyl, track, sect;
|
||||
uint32 ma;
|
||||
uint16 comp;
|
||||
RKCONTR comp;
|
||||
|
||||
drv = (int32) (uptr - rk_dev.units); /* get drv number */
|
||||
if (uptr->FUNC == RKCS_SEEK) { /* seek */
|
||||
@ -527,7 +543,7 @@ if ((da + wc) > (int32) uptr->capac) { /* overrun? */
|
||||
rker = rker | RKER_OVR; /* set overrun err */
|
||||
}
|
||||
|
||||
err = fseek (uptr->fileref, da * sizeof (int16), SEEK_SET);
|
||||
err = fseek (uptr->fileref, da * sizeof (RKCONTR), SEEK_SET);
|
||||
if (wc && (err == 0)) { /* seek ok? */
|
||||
switch (uptr->FUNC) { /* case on function */
|
||||
|
||||
@ -544,19 +560,19 @@ if (wc && (err == 0)) { /* seek ok? */
|
||||
} /* end for wc */
|
||||
} /* end if format */
|
||||
else { /* normal read */
|
||||
i = fxread (rkxb, sizeof (int16), wc, uptr->fileref);
|
||||
i = fxread (rkxb, sizeof (RKCONTR), wc, uptr->fileref);
|
||||
err = ferror (uptr->fileref); /* read file */
|
||||
for ( ; i < wc; i++) /* fill buf */
|
||||
rkxb[i] = 0;
|
||||
}
|
||||
if (rkcs & RKCS_INH) { /* incr inhibit? */
|
||||
if ((t = Map_WriteW (ma, 2, &rkxb[wc - 1]))) {/* store last */
|
||||
if ((t = MAP_WRW (ma, 2, &rkxb[wc - 1]))) { /* store last */
|
||||
rker = rker | RKER_NXM; /* NXM? set flag */
|
||||
wc = 0; /* no transfer */
|
||||
}
|
||||
}
|
||||
else { /* normal store */
|
||||
if ((t = Map_WriteW (ma, wc << 1, rkxb))) { /* store buf */
|
||||
if ((t = MAP_WRW (ma, wc << 1, rkxb))) { /* store buf */
|
||||
rker = rker | RKER_NXM; /* NXM? set flag */
|
||||
wc = wc - t; /* adj wd cnt */
|
||||
}
|
||||
@ -565,7 +581,7 @@ if (wc && (err == 0)) { /* seek ok? */
|
||||
|
||||
case RKCS_WRITE: /* write */
|
||||
if (rkcs & RKCS_INH) { /* incr inhibit? */
|
||||
if ((t = Map_ReadW (ma, 2, &comp))) { /* get 1st word */
|
||||
if ((t = MAP_RDW (ma, 2, &comp))) { /* get 1st word */
|
||||
rker = rker | RKER_NXM; /* NXM? set flag */
|
||||
wc = 0; /* no transfer */
|
||||
}
|
||||
@ -573,7 +589,7 @@ if (wc && (err == 0)) { /* seek ok? */
|
||||
rkxb[i] = comp;
|
||||
}
|
||||
else { /* normal fetch */
|
||||
if ((t = Map_ReadW (ma, wc << 1, rkxb))) { /* get buf */
|
||||
if ((t = MAP_RDW (ma, wc << 1, rkxb))) { /* get buf */
|
||||
rker = rker | RKER_NXM; /* NXM? set flg */
|
||||
wc = wc - t; /* adj wd cnt */
|
||||
}
|
||||
@ -582,13 +598,13 @@ if (wc && (err == 0)) { /* seek ok? */
|
||||
awc = (wc + (RK_NUMWD - 1)) & ~(RK_NUMWD - 1); /* clr to */
|
||||
for (i = wc; i < awc; i++) /* end of blk */
|
||||
rkxb[i] = 0;
|
||||
fxwrite (rkxb, sizeof (int16), awc, uptr->fileref);
|
||||
fxwrite (rkxb, sizeof (RKCONTR), awc, uptr->fileref);
|
||||
err = ferror (uptr->fileref);
|
||||
}
|
||||
break; /* end write */
|
||||
|
||||
case RKCS_WCHK: /* write check */
|
||||
i = fxread (rkxb, sizeof (int16), wc, uptr->fileref);
|
||||
i = fxread (rkxb, sizeof (RKCONTR), wc, uptr->fileref);
|
||||
if ((err = ferror (uptr->fileref))) { /* read error? */
|
||||
wc = 0; /* no transfer */
|
||||
break;
|
||||
@ -597,7 +613,7 @@ if (wc && (err == 0)) { /* seek ok? */
|
||||
rkxb[i] = 0;
|
||||
awc = wc; /* save wc */
|
||||
for (wc = 0, cma = ma; wc < awc; wc++) { /* loop thru buf */
|
||||
if (Map_ReadW (cma, 2, &comp)) { /* mem wd */
|
||||
if (MAP_RDW (cma, 2, &comp)) { /* mem wd */
|
||||
rker = rker | RKER_NXM; /* NXM? set flg */
|
||||
break;
|
||||
}
|
||||
@ -710,7 +726,7 @@ for (i = 0; i < RK_NUMDR; i++) {
|
||||
uptr->flags = uptr->flags & ~UNIT_SWLK;
|
||||
}
|
||||
if (rkxb == NULL)
|
||||
rkxb = (uint16 *) calloc (RK_MAXFR, sizeof (uint16));
|
||||
rkxb = (RKCONTR *) calloc (RK_MAXFR, sizeof (RKCONTR));
|
||||
if (rkxb == NULL)
|
||||
return SCPE_MEM;
|
||||
return SCPE_OK;
|
||||
@ -718,6 +734,15 @@ return SCPE_OK;
|
||||
|
||||
/* Device bootstrap */
|
||||
|
||||
#if defined (UC15)
|
||||
|
||||
t_stat rk_boot (int32 unitno, DEVICE *dptr)
|
||||
{
|
||||
return SCPE_NOFNC;
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
#define BOOT_START 02000 /* start */
|
||||
#define BOOT_ENTRY (BOOT_START + 002) /* entry */
|
||||
#define BOOT_UNIT (BOOT_START + 010) /* unit number */
|
||||
@ -753,6 +778,7 @@ static const uint16 boot_rom[] = {
|
||||
t_stat rk_boot (int32 unitno, DEVICE *dptr)
|
||||
{
|
||||
size_t i;
|
||||
extern uint16 *M; /* memory */
|
||||
|
||||
for (i = 0; i < BOOT_LEN; i++)
|
||||
M[(BOOT_START >> 1) + i] = boot_rom[i];
|
||||
@ -761,3 +787,5 @@ M[BOOT_CSR >> 1] = (rk_dib.ba & DMASK) + 012;
|
||||
cpu_set_boot (BOOT_ENTRY);
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
#endif
|
||||
@ -1,6 +1,6 @@
|
||||
/* pdp11_sys.c: PDP-11 simulator interface
|
||||
|
||||
Copyright (c) 1993-2013, Robert M Supnik
|
||||
Copyright (c) 1993-2016, Robert M Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
@ -23,6 +23,7 @@
|
||||
used in advertising or otherwise to promote the sale, use or other dealings
|
||||
in this Software without prior written authorization from Robert M Supnik.
|
||||
|
||||
14-Mar-16 RMS Added UC15 support
|
||||
02-Sep-13 RMS Added third Massbus, RS03/RS04
|
||||
29-Apr-12 RMS Fixed compiler warning (Mark Pizzolato)
|
||||
19-Nov-08 RMS Moved I/O support routines to I/O library
|
||||
@ -104,6 +105,7 @@ extern DEVICE xq_dev, xqb_dev;
|
||||
extern DEVICE xu_dev, xub_dev;
|
||||
extern DEVICE ke_dev;
|
||||
extern DEVICE kg_dev;
|
||||
extern DEVICE uca_dev, ucb_dev;
|
||||
extern UNIT cpu_unit;
|
||||
extern REG cpu_reg[];
|
||||
extern uint16 *M;
|
||||
@ -128,6 +130,7 @@ int32 sim_emax = 4;
|
||||
DEVICE *sim_devices[] = {
|
||||
&cpu_dev,
|
||||
&sys_dev,
|
||||
#if !defined (UC15)
|
||||
&mba_dev[0],
|
||||
&mba_dev[1],
|
||||
&mba_dev[2],
|
||||
@ -168,8 +171,18 @@ DEVICE *sim_devices[] = {
|
||||
&xqb_dev,
|
||||
&xu_dev,
|
||||
&xub_dev,
|
||||
&ke_dev,
|
||||
&kg_dev,
|
||||
&ke_dev,
|
||||
#else
|
||||
&clk_dev,
|
||||
&tti_dev,
|
||||
&tto_dev,
|
||||
&cr_dev,
|
||||
&lpt_dev,
|
||||
&rk_dev,
|
||||
&uca_dev,
|
||||
&ucb_dev,
|
||||
#endif
|
||||
NULL
|
||||
};
|
||||
|
||||
@ -249,11 +262,9 @@ do { /* block loop */
|
||||
if ((d = getc (fileref)) == EOF) /* data char */
|
||||
return SCPE_FMT;
|
||||
csum = csum + d; /* add into csum */
|
||||
if (org >= MEMSIZE) /* invalid addr? */
|
||||
if (!ADDR_IS_MEM (org)) /* invalid addr? */
|
||||
return SCPE_NXM;
|
||||
M[org >> 1] = (org & 1)? /* store data */
|
||||
(M[org >> 1] & 0377) | (uint16)(d << 8):
|
||||
(M[org >> 1] & 0177400) | (uint16)d;
|
||||
WrMemB (org, ((uint16) d));
|
||||
org = (org + 1) & 0177777; /* inc origin */
|
||||
}
|
||||
if ((d = getc (fileref)) == EOF) /* get csum */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user