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PDP11, PDP10, VAX780: CR11 is BR6, CD11 is BR4

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This commit is contained in:
Bob Supnik 2017-03-07 09:05:59 -08:00 committed by Mark Pizzolato
parent d7a98da256
commit ae3179e2fe
7 changed files with 115 additions and 46 deletions
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5
PDP10/pdp10_defs.h
View File

@ -1,6 +1,6 @@
/* pdp10_defs.h: PDP-10 simulator definitions
Copyright (c) 1993-2013, Robert M Supnik
Copyright (c) 1993-2017, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -23,6 +23,7 @@
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
19-Jan-17 RMS Fixed CD11 definition (Mark Pizzolatto)
30-Jun-13 RMS Fixed IPL4 mask definition (Tim Litt)
22-May-10 RMS Added check for 64b addresses
01-Feb-07 RMS Added CD support
@ -734,7 +735,7 @@ typedef struct pdp_dib DIB;
#define INT_PTR (1u << INT_V_PTR)
#define INT_PTP (1u << INT_V_PTP)
#define INT_LP20 (1u << INT_V_LP20)
#define INT_CR (1u << INT_V_CR)
#define INT_CR (1u << INT_V_CD)
#define INT_DUPRX (1u << INT_V_DUPRX)
#define INT_DUPTX (1u << INT_V_DUPTX)

16
PDP10/pdp10_ksio.c
View File

@ -1,6 +1,6 @@
/* pdp10_ksio.c: PDP-10 KS10 I/O subsystem simulator
Copyright (c) 1993-2013, Robert M Supnik
Copyright (c) 1993-2017, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -25,6 +25,7 @@
uba Unibus adapters
7-Mar-17 RMS Added BR level to vector display
27-May-13 RMS Fixed bugs in Unibus adapter code
22-Sep-05 RMS Fixed declarations (from Sterling Garwood)
25-Jan-04 RMS Added stub floating address routine
@ -114,6 +115,9 @@ static const int32 ubabr76[UBANUM] = {
static const int32 ubabr54[UBANUM] = {
INT_UB1 & (INT_IPL5 | INT_IPL4), INT_UB3 & (INT_IPL5 | INT_IPL4)
};
static const uint32 iplmask[4] = {
INT_IPL4, INT_IPL5, INT_IPL6, INT_IPL7
};
/* Masks for Unibus quantities */
#define M_BYTE (0xFF)
@ -1783,7 +1787,7 @@ t_stat show_vec (FILE *st, UNIT *uptr, int32 arg, void *desc)
{
DEVICE *dptr;
DIB *dibp;
uint32 vec, numvec;
uint32 i, j, vec, numvec, br_bit;
if (uptr == NULL)
return SCPE_IERR;
@ -1804,6 +1808,14 @@ else {
if (numvec > 1)
fprintf (st, "-%o", vec + (4 * (numvec - 1)));
}
br_bit = 1u << dibp->vloc;
for (i = 0, j = 4; i < 4; i++) {
if ((br_bit & iplmask[i]) != 0)
j = i;
}
if (j >= 4)
fprintf (st, ", invalid BR level");
else fprintf (st, ", BR%d", j + 4);
return SCPE_OK;
}

114
PDP11/pdp11_cr.c
View File

@ -1,6 +1,6 @@
/* pdp11_cr.c: CR/CM/CD-11/CD20 card reader simulator
Copyright (c) 2005-2016, John A. Dundas III
Copyright (c) 2005-2017, John A. Dundas III
Portions derived from work by Douglas W. Jones, jones@cs.uiowa.edu
Portions derived from work by Robert M Supnik
@ -100,6 +100,7 @@
ECOs (at least) for Data Buffer status and augmented image mode.
Revision History:
19-Jan-17 RMS CR11 is BR6, CD11 is BR4
14-Mar-16 RMS Added UC15 support (CR11 only)
30-Mar-15 RMS Backported from GitHub master; removed extended
help and Qbus support
@ -203,32 +204,44 @@
* known software support, as this reduces user configuration errors/confusion.
*/
#if defined (VM_PDP10) /* PDP10 version */
#include "pdp10_defs.h"
extern int32 int_req;
#define DFLT_DIS (DEV_DIS)
#define DFLT_TYPE (UNIT_CD20) /* CD20 (CD11) only */
#define CD20_ONLY (1)
#define IPL_CD (IPL_CR) /* use same for CD */
#define INT_V_CD (INT_V_CR)
#define INT_CD (INT_CR)
#define DFLT_QB (0)
#define DFLT_TYPE (UNIT_CD20) /* CD20 (CD11) only */
#define DFLT_IVCL (IVCL(CD))
#define DFLT_CPM 1200
#define CD20_ONLY (1)
#define AIECO_REQ (1) /* Requires Augmented Image ECO */
#elif defined (VM_VAX) /* VAX version */
#include "vax_defs.h"
extern int32 int_req[IPL_HLVL];
#define DFLT_DIS (DEV_QBUS) /* CR11 is programmed I/O only, Qbus OK */
#define IPL_CD (IPL_CR) /* use same for CD */
#define INT_V_CD (INT_V_CR)
#define INT_CD (INT_CR)
#define DFLT_QB (DEV_QBUS) /* CR11 is programmed I/O only, Qbus OK */
#define DFLT_TYPE (UNIT_CR11) /* CR11 only */
#define CR11_ONLY (1)
#define DFLT_IVCL (IVCL(CR))
#define DFLT_CPM 285
#define CR11_ONLY (1)
#else /* PDP-11 version */
#include "pdp11_defs.h"
extern int32 int_req[IPL_HLVL];
#define DFLT_DIS (DEV_QBUS) /* CR11 is programmed I/O only, Qbus OK */
#define DFLT_QB (DEV_QBUS) /* CR11 is programmed I/O only, Qbus OK */
#define DFLT_TYPE (UNIT_CR11) /* Default, but changable */
#define DFLT_IVCL (IVCL(CR))
#define DFLT_CPM 285
#define CR11_ONLY (1)
#if !defined (UC15)
#define CD11_OK (1) /* only on real PDP-11 */
#define CD20_OK (1)
#define AIECO_OK (1) /* Augmented Image ECO optional */
#if defined (UC15)
#define CR11_ONLY (1)
#else
#define CR11_OK (1) /* only on real PDP-11 */
#define CD11_OK (1)
#define CD20_OK (1)
#define AIECO_OK (1) /* Augmented Image ECO optional */
#endif
#endif
@ -241,7 +254,7 @@ extern int32 int_req[IPL_HLVL];
#define I4C_H82 I4C ('H','8','2',' ')
#define I4C_H40 I4C ('H','4','0',' ')
#define UNIT_V_TYPE (UNIT_V_UF + 0) /* Bit-encoded 2-bit field */
#define UNIT_V_TYPE (UNIT_V_UF + 0) /* Bit-encoded 2-bit field */
#define UNIT_TYPE (3u << UNIT_V_TYPE)
#define UNIT_CR11 (1u << UNIT_V_TYPE)
#define UNIT_CD20 (2u << UNIT_V_TYPE)
@ -466,7 +479,8 @@ t_stat cr_set_trans (UNIT *, int32, char*, void *);
t_stat cr_show_trans (FILE *, UNIT *, int32, void *);
static t_stat cr_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
const char *cr_description (DEVICE *dptr);
void cr_set_int (void);
void cr_clr_int (void);
/* CR data structures
@ -478,7 +492,7 @@ const char *cr_description (DEVICE *dptr);
*/
static DIB cr_dib = { IOBA_CR, IOLN_CR, &cr_rd, &cr_wr,
1, IVCL (CR), VEC_CR, { cr_intac } };
1, DFLT_IVCL, VEC_CR, { cr_intac } };
static UNIT cr_unit = {
UDATA (&cr_svc,
@ -493,21 +507,23 @@ static REG cr_reg[] = {
{ GRDATA (CRB1, crb1, DEV_RDX, 16, 0) },
{ GRDATA (CRB2, crb2, DEV_RDX, 16, 0) },
{ GRDATA (CRM, crm, DEV_RDX, 16, 0) },
{ FLDATA (INTCR, IREQ (CR), INT_V_CR) },
#endif
#if defined (CD11_OK) || defined (CD11_ONLY) || defined (CD20_OK) || defined (CD20_ONLY)
{ GRDATA (CDST, cdst, DEV_RDX, 16, 0) },
{ GRDATA (CDCC, cdcc, DEV_RDX, 16, 0) },
{ GRDATA (CDBA, cdba, DEV_RDX, 16, 0) },
{ GRDATA (CDDB, cddb, DEV_RDX, 16, 0) },
{ FLDATA (INTCD, IREQ (CD), INT_V_CD) },
#endif
{ GRDATA (BLOWER, blowerState, DEV_RDX, 2, 0) },
{ FLDATA (INT, IREQ (CR), INT_V_CR) },
{ FLDATA (ERR, crs, CSR_V_ERR) },
{ FLDATA (IE, crs, CSR_V_IE) },
{ DRDATA (POS, cr_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, cr_unit.wait, 24), PV_LEFT },
{ GRDATA (DEVADDR, cr_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVVEC, cr_dib.vec, DEV_RDX, 16, 0), REG_HRO },
{ GRDATA (DEVADDR, cr_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVVEC, cr_dib.vec, DEV_RDX, 16, 0), REG_HRO },
{ GRDATA (DEVVLOC, cr_dib.vloc, DEV_RDX, 16, 0), REG_HRO },
{ NULL } };
static char *translation_help = NULL;
@ -574,7 +590,7 @@ DEVICE cr_dev = {
1, 10, 31, 1, DEV_RDX, 8,
NULL, NULL, &cr_reset,
NULL, &cr_attach, &cr_detach,
&cr_dib, DEV_DISABLE | DFLT_DIS | DEV_UBUS | DEV_DEBUG
&cr_dib, DEV_DISABLE | DEV_DIS | DFLT_QB | DEV_UBUS | DEV_DEBUG
};
/* Utility routines */
@ -1025,7 +1041,7 @@ t_stat cr_wr ( int32 data,
if (access == WRITEB)
data = (crs & ~0377) | (data & 0377);
if (!(data & CSR_IE))
CLR_INT (CR);
cr_clr_int ();
crs = (crs & ~CRCSR_RW) | (data & CRCSR_RW);
/* Clear status bits after CSR load */
crs &= ~(CSR_ERR | CRCSR_ONLINE | CRCSR_CRDDONE | CRCSR_TIMERR);
@ -1042,7 +1058,7 @@ t_stat cr_wr ( int32 data,
if (curr_crs & (CRCSR_SUPPLY | CRCSR_RDCHK | CRCSR_OFFLINE)) {
crs |= CSR_ERR | (curr_crs & (CRCSR_SUPPLY | CRCSR_RDCHK |
CRCSR_OFFLINE));
if (crs & CSR_IE) SET_INT(CR);
if (crs & CSR_IE) cr_set_int ();
}
if (blowerState != BLOW_ON) {
blowerState = BLOW_START;
@ -1060,7 +1076,7 @@ t_stat cr_wr ( int32 data,
((data & 0x00ff) | (cdst & 0xFF00));
if (data & CDCSR_PWRCLR) {
CLR_INT (CR);
cr_clr_int ();
sim_cancel (&cr_unit);
cdcc = 0;
cdba = 0;
@ -1112,9 +1128,9 @@ t_stat cr_wr ( int32 data,
|(data & (CSR_ERR | CDCSR_RDRCHK | CDCSR_EOF | CDCSR_DATAERR | CDCSR_LATE |
CDCSR_NXM | CSR_IE | CDCSR_XBA17 | CDCSR_XBA16 | CDCSR_ONLINE | CDCSR_PACK));
}
/* Apparently the hardware does not SET_INT if ready/online are already set. If it did, TOPS-10's driver wouldn't work */
/* Apparently the hardware does not set int if ready/online are already set. If it did, TOPS-10's driver wouldn't work */
if (!(cdst & CSR_IE))
CLR_INT (CR);
cr_clr_int ();
if (DEBUG_PRS (cr_dev))
fprintf (sim_deb, "cr_wr data %06o cdst %06o\n",
@ -1206,7 +1222,7 @@ t_stat cr_svc ( UNIT *uptr )
/* (almost) anything we do now will cause a CR (But not a CD) interrupt */
if ((CR11_CTL(uptr)) && (crs & CSR_IE))
SET_INT (CR);
cr_set_int ();
/* Unit not attached, or error status while idle */
if (!(uptr->flags & UNIT_ATT) || (!(crs & CRCSR_BUSY) && ((CR11_CTL(uptr)?crs : cdst) & CSR_ERR))) {
@ -1216,7 +1232,7 @@ t_stat cr_svc ( UNIT *uptr )
cddbs |= CDDB_STACK;
}
if (cdst & CSR_IE)
SET_INT (CR);
cr_set_int ();
}
return (SCPE_OK);
}
@ -1233,7 +1249,7 @@ t_stat cr_svc ( UNIT *uptr )
/* Check CD11 error status that stops transfers */
if (CD11_CTL(uptr) && (cdst & (CDCSR_LATE | CDCSR_NXM))) {
cdst |= CSR_ERR | CDCSR_OFFLINE | CDCSR_RDY | CDCSR_RDRCHK;
SET_INT (CR);
cr_set_int ();
return (SCPE_OK);
}
@ -1243,7 +1259,7 @@ t_stat cr_svc ( UNIT *uptr )
/* If a CD11 gets this far, an interrupt is required. If CDCC != 0,
* continue reading the next card.
*/
SET_INT (CR);
cr_set_int ();
if (cdcc == 0)
return (SCPE_OK);
}
@ -1264,7 +1280,7 @@ readFault:
if (cdst & (CDCSR_RDRCHK | CDCSR_HOPPER))
cdst |= CSR_ERR | CDCSR_OFFLINE;
if (cdst & CSR_IE)
SET_INT (CR);
cr_set_int ();
} else {
/*
@ -1276,7 +1292,7 @@ readFault:
if (crs & (CRCSR_RDCHK | CRCSR_SUPPLY)) {
crs |= CSR_ERR | CRCSR_OFFLINE;
crs &= ~(CRCSR_ONLINE | CRCSR_BUSY | CRCSR_CRDDONE);
CLR_INT(CR);
cr_clr_int ();
}
}
sim_activate (uptr, spinDown);
@ -1392,13 +1408,13 @@ incremented properly. If this causes problems, I'll fix it.
* If this is the last column, defer interrupt so end doesn't interrupt again.
*/
if ((cdcc == 0) && (cdst & CSR_IE) && (currCol < colEnd))
SET_INT (CR);
cr_set_int ();
}
} else { /* CR11 */
/* Handle EJECT bit: if set DO NOT assert COLRDY */
/* nor interrupt */
if ((crs & CRCSR_EJECT)) {
CLR_INT (CR);
cr_clr_int ();
} else {
crs |= CRCSR_COLRDY;
}
@ -1484,6 +1500,7 @@ t_stat cr_reset ( DEVICE *dptr )
}
EOFcard = 0;
CLR_INT (CR);
CLR_INT (CD);
/* TBD: flush current card */
/* init uptr->wait ? */
return auto_config (dptr->name, 1);
@ -1533,6 +1550,29 @@ t_stat cr_detach ( UNIT *uptr )
return (detach_unit (uptr));
}
void cr_set_int (void)
{
if (CR11_CTL (&cr_unit)) {
SET_INT (CR);
}
else {
SET_INT (CD);
}
return;
}
void cr_clr_int (void)
{
if (CR11_CTL (&cr_unit)) {
CLR_INT (CR);
}
else {
CLR_INT (CD);
}
return;
}
#if defined (CR11_OK) || defined (CD11_OK) || defined (CD20_OK)
t_stat cr_set_type ( UNIT *uptr,
int32 val,
@ -1540,15 +1580,21 @@ t_stat cr_set_type ( UNIT *uptr,
void *desc )
{
DEVICE *dptr = find_dev_from_unit (uptr);
DIB *dibp;
/* disallow type change if currently attached */
if (uptr->flags & UNIT_ATT)
return (SCPE_NOFNC);
if (dptr == NULL)
return (SCPE_IERR);
if ((dibp = (DIB *) dptr->ctxt) == NULL)
return (SCPE_IERR);
cpm = (val & UNIT_CR11) ? 285 : ((val & UNIT_CD20)? 1200 :1000);
uptr->wait = (60 * 1000000) / (cpm * 80); /* Time between columns in usec.
* Readers are rated in card/min for 80 column cards */
transcodes[0].table = (val & UNIT_CD20)? o29_decascii_code : o29_code;
dibp->vloc = (val & UNIT_CR11)? IVCL (CR): IVCL (CD);
return (SCPE_OK);
}
@ -1648,7 +1694,7 @@ t_stat cr_set_reset ( UNIT *uptr,
/* Assert interrupt if interrupts enabled */
if ((CR11_CTL(uptr)?crs : cdst) & CSR_IE) {
SET_INT (CR);
cr_set_int ();
if (DEBUG_PRS (cr_dev))
fprintf (sim_deb, "cr_set_reset setting interrupt\n");
}
@ -1687,7 +1733,7 @@ t_stat cr_set_stop ( UNIT *uptr,
cdst |= CSR_ERR | CDCSR_OFFLINE;
/* CD11 does not appear to interrupt on STOP. */
if (CR11_CTL(uptr) && (crs & CSR_IE))
SET_INT (CR);
cr_set_int ();
if (blowerState != BLOW_OFF) {
blowerState = BLOW_STOP;
}

12
PDP11/pdp11_defs.h
View File

@ -26,7 +26,8 @@
The author gratefully acknowledges the help of Max Burnet, Megan Gentry,
and John Wilson in resolving questions about the PDP-11
06-Jan-17 RMS Moved CR11/CD11 to BR6 (Mark Pizzolato)
10-Feb-17 RMS Fixed RJS11 register block length (Mark Hill)
19-Jan-17 RMS Moved CR11 to BR6, leaving CD11 at BR4 (Mark Pizzolato)
10-Mar-16 RMS Added UC15 support
30-Dec-15 RMS Added NOBVT option
23-Oct-13 RMS Added cpu_set_boot prototype
@ -655,7 +656,7 @@ typedef struct pdp_dib DIB;
#define INT_V_PCLK 2
#define INT_V_DTA 3
#define INT_V_TA 4
#define INT_V_CR 5
#define INT_V_CR 5 /* CR11 */
#define INT_V_PIR5 0 /* BR5 */
#define INT_V_RK 1
@ -686,7 +687,7 @@ typedef struct pdp_dib DIB;
#define INT_V_LPT 5
#define INT_V_VHRX 6
#define INT_V_VHTX 7
// #define XXX 8 /* former CR */
#define INT_V_CD 8 /* CD11 */
#define INT_V_DLI 9
#define INT_V_DLO 10
#define INT_V_DCI 11
@ -703,6 +704,7 @@ typedef struct pdp_dib DIB;
#define INT_PCLK (1u << INT_V_PCLK)
#define INT_DTA (1u << INT_V_DTA)
#define INT_TA (1u << INT_V_TA)
#define INT_CR (1u << INT_V_CR)
#define INT_PIR5 (1u << INT_V_PIR5)
#define INT_RK (1u << INT_V_RK)
#define INT_RL (1u << INT_V_RL)
@ -731,7 +733,7 @@ typedef struct pdp_dib DIB;
#define INT_LPT (1u << INT_V_LPT)
#define INT_VHRX (1u << INT_V_VHRX)
#define INT_VHTX (1u << INT_V_VHTX)
#define INT_CR (1u << INT_V_CR)
#define INT_CD (1u << INT_V_CD)
#define INT_DLI (1u << INT_V_DLI)
#define INT_DLO (1u << INT_V_DLO)
#define INT_DCI (1u << INT_V_DCI)
@ -780,6 +782,7 @@ typedef struct pdp_dib DIB;
#define IPL_LPT 4
#define IPL_VHRX 4
#define IPL_VHTX 4
#define IPL_CD 4
#define IPL_DLI 4
#define IPL_DLO 4
#define IPL_DCI 4
@ -830,6 +833,7 @@ typedef struct pdp_dib DIB;
#define VEC_DZRX 0300
#define VEC_DZTX 0304
#define VEC_VHRX 0310
#define VEC_CD 0230
#define VEC_VHTX 0314
#define VEC_UCA 0300
#define VEC_UCB 0310

8
PDP11/pdp11_io_lib.c
View File

@ -1,6 +1,6 @@
/* pdp11_io_lib.c: Unibus/Qbus common support routines
Copyright (c) 1993-2008, Robert M Supnik
Copyright (c) 1993-2017, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -190,7 +190,7 @@ t_stat show_vec (FILE *st, UNIT *uptr, int32 arg, void *desc)
{
DEVICE *dptr;
DIB *dibp;
uint32 vec, numvec, radix = DEV_RDX;
uint32 vec, numvec, br_lvl, radix = DEV_RDX;
if (uptr == NULL)
return SCPE_IERR;
@ -228,6 +228,10 @@ else {
}
}
}
br_lvl = dibp->vloc / 32;
if (br_lvl < 4) /* VAXen do 0-3, others 4-7 */
br_lvl = br_lvl + 4;
fprintf (st, ", BR%d", br_lvl);
return SCPE_OK;
}

3
PDP11/pdp11_io_lib.h
View File

@ -1,6 +1,6 @@
/* pdp11_io_lib.h: Unibus/Qbus common support routines header file
Copyright (c) 1993-2008, Robert M Supnik
Copyright (c) 1993-2017, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -35,6 +35,7 @@ t_stat set_addr_flt (UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat set_vec (UNIT *uptr, int32 arg, char *cptr, void *desc);
t_stat show_vec (FILE *st, UNIT *uptr, int32 arg, void *desc);
t_stat show_vec_mux (FILE *st, UNIT *uptr, int32 arg, void *desc);
t_stat show_br (FILE *st, UNIT *uptr, int32 arg, void *desc);
t_stat show_iospace (FILE *st, UNIT *uptr, int32 val, void *desc);
t_stat auto_config (char *name, int32 nctrl);
t_stat pdp11_bad_block (UNIT *uptr, int32 sec, int32 wds);

3
VAX/vax780_defs.h
View File

@ -23,7 +23,7 @@
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
06-Jan-17 RMS Moved CR to BR6 (Mark Pizzolato)
19-Jan-17 RMS Moved CR to BR6 (Mark Pizzolato)
29-Mar-15 RMS Added model specific IPR max
16-Dec-14 RMS Removed TQ boot code (780 VMB doesn't support tape boot)
05-Sep-14 RMS Fixed SBR test (found by Mark Pizzolato)
@ -320,6 +320,7 @@ typedef struct {
#define IOLN_PTP 004
/* Interrupt assignments; within each level, priority is right to left */
/* CD11 must be defined but is not allowed in the configuration */
#define INT_V_CR 0 /* BR6 */