Mark Pizzolato 3eadc405d0 PDP10: Ignore 0 value writes to the timer interval register ...

This avoids a divide by zero which is never right, but it is unclear
what the real hardware did.  It wouldn't be useful in any case.

As discussed in #486

2017-11-14 18:47:05 -08:00

..

pdp10_bug_history.txt

PDP10: Fix nested indirect address limit exceeded (from Bob Supnik)

2016-02-19 12:28:56 -08:00

pdp10_cpu.c

H316, I7094, NOVA, PDP1, PDP10, PDP8, SDS: Coverity singleton errors

2017-09-07 09:59:04 -07:00

pdp10_defs.h

PDP11, PDP10, VAX780: CR11 is BR6, CD11 is BR4

2017-03-07 09:42:37 -08:00

pdp10_fe.c

SCP: Removed KBD_WAIT and friends

2017-03-20 22:33:38 -07:00

pdp10_ksio.c

PDP11, PDP10, VAX780: CR11 is BR6, CD11 is BR4

2017-03-07 09:42:37 -08:00

pdp10_lp20.c

PDP11, PDP10, all VAX: General extern cleanup.

2017-02-04 19:37:20 -08:00

pdp10_mdfp.c

PDP11, PDP10, all VAX: General extern cleanup.

2017-02-04 19:37:20 -08:00

pdp10_pag.c

PDP11, PDP10, all VAX: General extern cleanup.

2017-02-04 19:37:20 -08:00

pdp10_rp.c

PDP10: Add fall through comment to case (COVERITY)

2017-03-28 19:27:27 -07:00

pdp10_sys.c

PDP10: Fixed word count test in EXE loader (COVERITY)

2017-03-09 20:09:59 -08:00

pdp10_tim.c

PDP10: Ignore 0 value writes to the timer interval register

2017-11-14 18:47:05 -08:00

pdp10_tu.c

PDP10: Documented switch fall through case (COVERITY)

2017-03-28 14:32:10 -07:00

pdp10_xtnd.c

PDP11, PDP10, all VAX: General extern cleanup.

2017-02-04 19:37:20 -08:00