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7a68c268b92445aab431d9905e47518c180dd27b
The code in 3.12-2 is only part of a complete solution and thus merely hangs the device/processor. The reverted version wouldn't normally have the problem since the normally partial code was trying to fix since I/O completion happens right in dz_wr(). However, the "complete it immediately" model could logically lose data if the sending side were driven harder than the TMXR TCP transport was able to deliver data to the TCP session. The easiest answer is to revert to the earlier v3 DZ code since at least that worked almost all of the time. The right answer would be to only signal the transmit completion interrupt if the transmit didn't end up getting buffered and if it did get buffered (and not successfully flushed), then schedule a separate unit to retry the pending output until it actually made it to the TCP wire. That separate unit would then signal the interrupt for the line indicated in the CSR and mark CSR_TRDY. This is more change to realize relatively little value so simply revert and be done.
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The Open SIMH simulators package
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