90e4597aa9
Adds 6850 DCD status latch to M2SIO devices. Adds vector interrupt support to M2SIO devices. Removes CTS inactive transmit disable from PMMI device. Adds IMSAI-style programmed output to CPU/SIO devices. SET CPU PO will display "PO: AREG" upon an "OUT 0FFH" instruction. SET CPU NOPO will disable the function (default). Corrects problem with Mode 0 interrupts. When the CPU receives an interrupt, it pushes the current program counter on the stack. The current implementation of Mode 0 was performing interrupt processing after fetching the next opcode from RAM, which also increases the PC by 1. This caused PC+1 to be pushed on the stack. The interrupt processing is now done prior to fetching the next opcode, preserving the correct program counter.
Open SIMH machine simulator
This is the codebase of SIMH, a framework and collection of computer system simulators.
SIMH was created by Bob Supnik, originally at Digital Equipment Corporation, and extended by contributions of many other people. It is now an open source project, licensed under an MIT open source license (see LICENSE.txt for the specific wording). The project gatekeepers are the members of the SIMH Steering Group. We welcome and encourage contributions from all. Contributions will be covered by the project license.
The Open SIMH code base was taken from a code base maintained by Mark Pizzolato as of 12 May 2022. From that point onward there is no connection between that source and the Open SIMH code base. A detailed listing of features as of that point may be found in SIMH-V4-status.
PLEASE NOTE
Do not contribute material taken from github.com/simh/simh unless you are the author of the material in question.