mirror of
https://github.com/open-simh/simtools.git
synced 2026-03-03 18:16:30 +00:00
Allow implicit floating point immediate for FPP instructions
which have an general (source) argument and an AC destination. There are no FPP instrs which have 1 general source arg; only with 1 general destination (even TSTF).
This commit is contained in:
36
assemble.c
36
assemble.c
@@ -30,6 +30,8 @@
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/* This function is way way too large, because I just coded most of
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the operation code and pseudo-op handling right in line. */
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/* FIXME: nobody checks for extra junk after a valid statement */
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static int assemble(
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STACK *stack,
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TEXT_RLD *tr)
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@@ -1605,6 +1607,31 @@ static int assemble(
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}
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return 1;
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#if 0
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/*
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* Although it is arguable that the FPP TSTF/TSTD instruction has 1
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* operand which is a floating point source, the PDP11 Architecture
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* Handbook describes it as a destination, and MACRO11 V05.05 doesn't
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* allow a FP literal argument.
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*/
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case OC_FPPSRC:
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/* One fp immediate or a general addressing mode */ {
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ADDR_MODE mode;
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unsigned word;
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if (!get_fp_src_mode(cp, &cp, &mode)) {
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report(stack->top, "Illegal addressing mode\n");
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return 0;
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}
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/* Build instruction word */
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word = op->value | mode.type;
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store_word(stack->top, tr, 2, word);
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mode_extension(tr, &mode, stack->top);
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}
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return 1;
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#endif
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case OC_FPPGENAC:
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/* One one gen and one reg 0-3 */ {
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ADDR_MODE mode;
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@@ -1612,7 +1639,7 @@ static int assemble(
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unsigned reg;
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unsigned word;
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if (!get_mode(cp, &cp, &mode)) {
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if (!get_fp_src_mode(cp, &cp, &mode)) {
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report(stack->top, "Illegal addressing mode\n");
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return 0;
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}
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@@ -1635,7 +1662,7 @@ static int assemble(
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/*
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* We could check here that the general mode
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* is not R6 or R7, but the original Macro11
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* is not AC6 or AC7, but the original Macro11
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* doesn't do that either.
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*/
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word = op->value | mode.type | (reg << 6);
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@@ -1676,8 +1703,11 @@ static int assemble(
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/*
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* We could check here that the general mode
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* is not R6 or R7, but the original Macro11
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* is not AC6 or AC7, but the original Macro11
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* doesn't do that either.
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*
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* For some (mostly STore instructions) the
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* destination isn't a FDST but a plain DST.
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*/
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word = op->value | mode.type | (reg << 6);
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store_word(stack->top, tr, 2, word);
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39
parse.c
39
parse.c
@@ -318,6 +318,45 @@ int get_mode(
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return TRUE;
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}
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/* get_fp_src_mode - parse an immediate fp literal or a general mode */
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int get_fp_src_mode(
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char *cp,
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char **endp,
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ADDR_MODE *mode)
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{
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cp = skipwhite(cp);
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char *savecp = cp;
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if (cp[0] == '#') {
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unsigned flt[1];
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char *fltendp = NULL;
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cp = skipwhite(cp + 1);
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int ret = parse_float(cp, &fltendp, 1, flt);
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if (ret) {
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mode->type = 027;
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mode->rel = 0;
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mode->offset = new_ex_lit(flt[0]);
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mode->offset->cp = fltendp;
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if (endp)
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*endp = mode->offset->cp;
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return TRUE;
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} else if (fltendp) {
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/* it looked like a fp number but something was wrong with it */
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}
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}
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int ret = get_mode(savecp, endp, mode);
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return ret;
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}
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#define DEBUG_FLOAT 0
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#if DEBUG_FLOAT
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4
parse.h
4
parse.h
@@ -37,6 +37,10 @@ int get_mode(
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char *cp,
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char **endp,
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ADDR_MODE *mode);
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int get_fp_src_mode(
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char *cp,
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char **endp,
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ADDR_MODE *mode);
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EX_TREE *parse_expr(
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char *cp,
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17
symbols.c
17
symbols.c
@@ -414,13 +414,14 @@ void add_symbols(
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add_sym("XOR", I_XOR, OC_JSR, &instruction_section, &system_st);
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add_sym("MFPT", I_MFPT, OC_NONE, &instruction_section, &system_st);
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add_sym("ABSD", I_ABSD, OC_1GEN, &instruction_section, &system_st);
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add_sym("ABSF", I_ABSF, OC_1GEN, &instruction_section, &system_st);
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/* FPP instructions */
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add_sym("ABSD", I_ABSD, OC_FPPDST, &instruction_section, &system_st);
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add_sym("ABSF", I_ABSF, OC_FPPDST, &instruction_section, &system_st);
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add_sym("ADDD", I_ADDD, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("ADDF", I_ADDF, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("CFCC", I_CFCC, OC_NONE, &instruction_section, &system_st);
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add_sym("CLRD", I_CLRD, OC_1GEN, &instruction_section, &system_st);
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add_sym("CLRF", I_CLRF, OC_1GEN, &instruction_section, &system_st);
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add_sym("CLRD", I_CLRD, OC_FPPDST, &instruction_section, &system_st);
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add_sym("CLRF", I_CLRF, OC_FPPDST, &instruction_section, &system_st);
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add_sym("CMPD", I_CMPD, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("CMPF", I_CMPF, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("DIVD", I_DIVD, OC_FPPGENAC, &instruction_section, &system_st);
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@@ -438,8 +439,8 @@ void add_symbols(
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add_sym("MODF", I_MODF, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("MULD", I_MULD, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("MULF", I_MULF, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("NEGD", I_NEGD, OC_1GEN, &instruction_section, &system_st);
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add_sym("NEGF", I_NEGF, OC_1GEN, &instruction_section, &system_st);
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add_sym("NEGD", I_NEGD, OC_FPPDST, &instruction_section, &system_st);
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add_sym("NEGF", I_NEGF, OC_FPPDST, &instruction_section, &system_st);
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add_sym("SETD", I_SETD, OC_NONE, &instruction_section, &system_st);
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add_sym("SETF", I_SETF, OC_NONE, &instruction_section, &system_st);
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add_sym("SETI", I_SETI, OC_NONE, &instruction_section, &system_st);
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@@ -459,8 +460,8 @@ void add_symbols(
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add_sym("STST", I_STST, OC_1GEN, &instruction_section, &system_st);
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add_sym("SUBD", I_SUBD, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("SUBF", I_SUBF, OC_FPPGENAC, &instruction_section, &system_st);
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add_sym("TSTD", I_TSTD, OC_1GEN, &instruction_section, &system_st);
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add_sym("TSTF", I_TSTF, OC_1GEN, &instruction_section, &system_st);
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add_sym("TSTD", I_TSTD, OC_FPPDST, &instruction_section, &system_st);
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add_sym("TSTF", I_TSTF, OC_FPPDST, &instruction_section, &system_st);
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/* FIXME: The CIS instructions are missing! */
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@@ -283,6 +283,10 @@ enum operand_codes { OC_MASK = 0xff00,
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/* FPP (gen, floating ac 0-3) */
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OC_FPPACGEN = 0x0a00,
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/* FPP (floating ac 0-3, gen) */
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OC_FPPSRC = 0x0b00,
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/* FPP fp source: immediate or gen */
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OC_FPPDST = OC_1GEN,
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/* FPP general destination */
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OC__LAST = 0xff00
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};
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@@ -121,16 +121,45 @@
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99 000340 077777 177777 177777 .FLT4 170141183460469230564930741053754966016 ; 2**127-(2**70-2**64+2**62+2)
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000346 177777
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100
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101 .end
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101
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101 ; Several ways to define a name for the fpp registers
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102 ; TODO: change symbol table to show % sign
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103
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104 000000 ac0 = r0
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105 000001 ac1 = %1
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106 000002 f2 = %2
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107
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108 000350 171003 mulf r3,ac0
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109 000352 171102 mulf r2,ac1
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110 000354 172227 041040 ADDF #^O41040,F2
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111 000360 172127 040200 addf #1,ac1
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112
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113 000364 171003 mulf r3,ac0
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114 000366 171102 mulf r2,ac1
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115 000370 172227 041040 addf #^O41040,F2 ; taken literally
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116 000374 172127 040200 addf #1,ac1 ; as float
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117 000400 172127 040200 addf #1.,ac1 ; as float
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118 000404 172127 000001 addf #^D1,ac1 ; literally
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119 000410 172127 000002 addf #<1+1>,ac1 ; literally
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120 000414 172127 040300 addf #1.5,ac1 ; as float
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121 000420 172127 140263 addd #-1.4,ac1 ; as float
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122
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123 ; TODO: let parser check for junk at end of line
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124 000424 170627 000002 absf #2.5 ; bad: operand is destination
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125 000430 170527 000002 tstd #2.5 ; bad: operand is considered FDST by the arch handbook
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126 000434 174027 000002 stf ac0,#2.5 ; bad: junk at end of line
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127 000440 174027 000002 stf ac0,#2 ; doesn't makes sense but MACRO11 allows it
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128
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129
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130 .end
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130
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Symbol table
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. ******R 001
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. ******R 001 AC0 =000000 AC1 =000001 F2 =000002
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Program sections:
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. ABS. 000000 000 (RW,I,GBL,ABS,OVR,NOSAV)
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000350 001 (RW,I,LCL,REL,CON,NOSAV)
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000444 001 (RW,I,LCL,REL,CON,NOSAV)
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@@ -98,4 +98,33 @@
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.FLT4 170141183460469230564930741053754966015 ; 2**127-(2**70-2**64+2**62+1)
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.FLT4 170141183460469230564930741053754966016 ; 2**127-(2**70-2**64+2**62+2)
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; Several ways to define a name for the fpp registers
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; TODO: change symbol table to show % sign
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ac0 = r0
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ac1 = %1
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f2 = %2
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mulf r3,ac0
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mulf r2,ac1
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ADDF #^O41040,F2
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addf #1,ac1
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mulf r3,ac0
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mulf r2,ac1
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addf #^O41040,F2 ; taken literally
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addf #1,ac1 ; as float
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addf #1.,ac1 ; as float
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addf #^D1,ac1 ; literally
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addf #<1+1>,ac1 ; literally
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addf #1.5,ac1 ; as float
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addd #-1.4,ac1 ; as float
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; TODO: let parser check for junk at end of line
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absf #2.5 ; bad: operand is destination
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tstd #2.5 ; bad: operand is considered FDST by the arch handbook
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stf ac0,#2.5 ; bad: junk at end of line
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stf ac0,#2 ; doesn't makes sense but MACRO11 allows it
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.end
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