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Merge pull request #40 from LarsAsplund/master

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Setup GitHub Actions to ensure VHDL correctness of all code updates
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openpowerwtf 2021-05-23 07:01:33 -05:00 committed by GitHub
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25 changed files with 632 additions and 236 deletions
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13
.github/workflows/vunit_tests.yml vendored Normal file
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@ -0,0 +1,13 @@
name: VUnit Tests
on: [push, pull_request]
jobs:
test:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- uses: srt32/git-actions@v0.0.3
with:
args: git update-index --chmod=+x run.py
- uses: VUnit/vunit_action@master
with:
cmd: python3 ./run.py

6
README.md
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@ -1,3 +1,5 @@
![](https://github.com/openpower-cores/a2i/workflows/VUnit%20Tests/badge.svg)
# A2I
## The Project
@ -8,7 +10,7 @@ See [Project Info](rel/readme.md) for details.
## The Core
The [A2I core](rel/doc/A2_BGQ.pdf) was created as a high-frequency four-threaded design, optimized for throughput and targeted for 3+ GHz in 45nm technology.
It is a 27 FO4 implementation, with an in-order pipeline supporting 1-4 threads. It fully supports Power ISA 2.06 using Book III-E. The core was also designed to support pluggable implementations of MMU and AXU logic macros. This includes elimination of the MMU and using ERAT-only mode for translation/protection.
It is a 27 FO4 implementation, with an in-order pipeline supporting 1-4 threads. It fully supports Power ISA 2.06 using Book III-E. The core was also designed to support pluggable implementations of MMU and AXU logic macros. This includes elimination of the MMU and using ERAT-only mode for translation/protection.
## The History
@ -27,7 +29,7 @@ There may be uses for this core where a full feature-set is needed, and its limi
The design of the A2L2 interface (core-to-L2/nest) is straightforward, and offers multiple configurable options for data interfacing. There is also some configurability for handling certain Power-specific features (core vs. L2).
The ability to add an AXU that is tightly-coupled to the core enables many possibilities for special-purpose designs, like an open distributed Web 3.0 hardware/software system integrating streaming encryption, blockchain, semantic query, etc.
The ability to add an AXU that is tightly-coupled to the core enables many possibilities for special-purpose designs, like an open distributed Web 3.0 hardware/software system integrating streaming encryption, blockchain, semantic query, etc.
### Technology Scaling

185
rel/sim/unimacro/bram_tdp_macro_mock.vhdl Normal file
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library ieee;
use ieee.std_logic_1164.all;
entity BRAM_TDP_MACRO is
generic (
BRAM_SIZE : string;
DEVICE : string;
DOA_REG : integer;
DOB_REG : integer;
INIT_A : bit_vector;
INIT_B : bit_vector;
INIT_FILE : string;
READ_WIDTH_A : integer;
READ_WIDTH_B : integer;
SIM_COLLISION_CHECK : string;
SRVAL_A : bit_vector;
SRVAL_B : bit_vector;
WRITE_MODE_A : string;
WRITE_MODE_B : string;
WRITE_WIDTH_A : integer;
WRITE_WIDTH_B : integer;
INIT_00 : bit_vector;
INIT_01 : bit_vector;
INIT_02 : bit_vector;
INIT_03 : bit_vector;
INIT_04 : bit_vector;
INIT_05 : bit_vector;
INIT_06 : bit_vector;
INIT_07 : bit_vector;
INIT_08 : bit_vector;
INIT_09 : bit_vector;
INIT_0A : bit_vector;
INIT_0B : bit_vector;
INIT_0C : bit_vector;
INIT_0D : bit_vector;
INIT_0E : bit_vector;
INIT_0F : bit_vector;
INIT_10 : bit_vector;
INIT_11 : bit_vector;
INIT_12 : bit_vector;
INIT_13 : bit_vector;
INIT_14 : bit_vector;
INIT_15 : bit_vector;
INIT_16 : bit_vector;
INIT_17 : bit_vector;
INIT_18 : bit_vector;
INIT_19 : bit_vector;
INIT_1A : bit_vector;
INIT_1B : bit_vector;
INIT_1C : bit_vector;
INIT_1D : bit_vector;
INIT_1E : bit_vector;
INIT_1F : bit_vector;
INIT_20 : bit_vector;
INIT_21 : bit_vector;
INIT_22 : bit_vector;
INIT_23 : bit_vector;
INIT_24 : bit_vector;
INIT_25 : bit_vector;
INIT_26 : bit_vector;
INIT_27 : bit_vector;
INIT_28 : bit_vector;
INIT_29 : bit_vector;
INIT_2A : bit_vector;
INIT_2B : bit_vector;
INIT_2C : bit_vector;
INIT_2D : bit_vector;
INIT_2E : bit_vector;
INIT_2F : bit_vector;
INIT_30 : bit_vector;
INIT_31 : bit_vector;
INIT_32 : bit_vector;
INIT_33 : bit_vector;
INIT_34 : bit_vector;
INIT_35 : bit_vector;
INIT_36 : bit_vector;
INIT_37 : bit_vector;
INIT_38 : bit_vector;
INIT_39 : bit_vector;
INIT_3A : bit_vector;
INIT_3B : bit_vector;
INIT_3C : bit_vector;
INIT_3D : bit_vector;
INIT_3E : bit_vector;
INIT_3F : bit_vector;
INIT_40 : bit_vector;
INIT_41 : bit_vector;
INIT_42 : bit_vector;
INIT_43 : bit_vector;
INIT_44 : bit_vector;
INIT_45 : bit_vector;
INIT_46 : bit_vector;
INIT_47 : bit_vector;
INIT_48 : bit_vector;
INIT_49 : bit_vector;
INIT_4A : bit_vector;
INIT_4B : bit_vector;
INIT_4C : bit_vector;
INIT_4D : bit_vector;
INIT_4E : bit_vector;
INIT_4F : bit_vector;
INIT_50 : bit_vector;
INIT_51 : bit_vector;
INIT_52 : bit_vector;
INIT_53 : bit_vector;
INIT_54 : bit_vector;
INIT_55 : bit_vector;
INIT_56 : bit_vector;
INIT_57 : bit_vector;
INIT_58 : bit_vector;
INIT_59 : bit_vector;
INIT_5A : bit_vector;
INIT_5B : bit_vector;
INIT_5C : bit_vector;
INIT_5D : bit_vector;
INIT_5E : bit_vector;
INIT_5F : bit_vector;
INIT_60 : bit_vector;
INIT_61 : bit_vector;
INIT_62 : bit_vector;
INIT_63 : bit_vector;
INIT_64 : bit_vector;
INIT_65 : bit_vector;
INIT_66 : bit_vector;
INIT_67 : bit_vector;
INIT_68 : bit_vector;
INIT_69 : bit_vector;
INIT_6A : bit_vector;
INIT_6B : bit_vector;
INIT_6C : bit_vector;
INIT_6D : bit_vector;
INIT_6E : bit_vector;
INIT_6F : bit_vector;
INIT_70 : bit_vector;
INIT_71 : bit_vector;
INIT_72 : bit_vector;
INIT_73 : bit_vector;
INIT_74 : bit_vector;
INIT_75 : bit_vector;
INIT_76 : bit_vector;
INIT_77 : bit_vector;
INIT_78 : bit_vector;
INIT_79 : bit_vector;
INIT_7A : bit_vector;
INIT_7B : bit_vector;
INIT_7C : bit_vector;
INIT_7D : bit_vector;
INIT_7E : bit_vector;
INIT_7F : bit_vector;
INITP_00 : bit_vector;
INITP_01 : bit_vector;
INITP_02 : bit_vector;
INITP_03 : bit_vector;
INITP_04 : bit_vector;
INITP_05 : bit_vector;
INITP_06 : bit_vector;
INITP_07 : bit_vector;
INITP_08 : bit_vector;
INITP_09 : bit_vector;
INITP_0A : bit_vector;
INITP_0B : bit_vector;
INITP_0C : bit_vector;
INITP_0D : bit_vector;
INITP_0E : bit_vector;
INITP_0F : bit_vector
);
port (
DOA : out std_logic_vector;
DOB : out std_logic_vector;
ADDRA : in std_logic_vector;
ADDRB : in std_logic_vector;
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector;
DIB : in std_logic_vector;
ENA : in std_ulogic;
ENB : in std_ulogic;
REGCEA : in std_ulogic;
REGCEB : in std_ulogic;
RSTA : in std_ulogic;
RSTB : in std_ulogic;
WEA : in std_logic_vector;
WEB : in std_logic_vector
);
end entity;

187
rel/sim/unimacro/unimacro_vcomp_mock.vhdl Normal file
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@ -0,0 +1,187 @@
library ieee;
use ieee.std_logic_1164.all;
package vcomponents is
component BRAM_TDP_MACRO
generic (
BRAM_SIZE : string;
DEVICE : string;
DOA_REG : integer;
DOB_REG : integer;
INIT_A : bit_vector;
INIT_B : bit_vector;
INIT_FILE : string;
READ_WIDTH_A : integer;
READ_WIDTH_B : integer;
SIM_COLLISION_CHECK : string;
SRVAL_A : bit_vector;
SRVAL_B : bit_vector;
WRITE_MODE_A : string;
WRITE_MODE_B : string;
WRITE_WIDTH_A : integer;
WRITE_WIDTH_B : integer;
INIT_00 : bit_vector;
INIT_01 : bit_vector;
INIT_02 : bit_vector;
INIT_03 : bit_vector;
INIT_04 : bit_vector;
INIT_05 : bit_vector;
INIT_06 : bit_vector;
INIT_07 : bit_vector;
INIT_08 : bit_vector;
INIT_09 : bit_vector;
INIT_0A : bit_vector;
INIT_0B : bit_vector;
INIT_0C : bit_vector;
INIT_0D : bit_vector;
INIT_0E : bit_vector;
INIT_0F : bit_vector;
INIT_10 : bit_vector;
INIT_11 : bit_vector;
INIT_12 : bit_vector;
INIT_13 : bit_vector;
INIT_14 : bit_vector;
INIT_15 : bit_vector;
INIT_16 : bit_vector;
INIT_17 : bit_vector;
INIT_18 : bit_vector;
INIT_19 : bit_vector;
INIT_1A : bit_vector;
INIT_1B : bit_vector;
INIT_1C : bit_vector;
INIT_1D : bit_vector;
INIT_1E : bit_vector;
INIT_1F : bit_vector;
INIT_20 : bit_vector;
INIT_21 : bit_vector;
INIT_22 : bit_vector;
INIT_23 : bit_vector;
INIT_24 : bit_vector;
INIT_25 : bit_vector;
INIT_26 : bit_vector;
INIT_27 : bit_vector;
INIT_28 : bit_vector;
INIT_29 : bit_vector;
INIT_2A : bit_vector;
INIT_2B : bit_vector;
INIT_2C : bit_vector;
INIT_2D : bit_vector;
INIT_2E : bit_vector;
INIT_2F : bit_vector;
INIT_30 : bit_vector;
INIT_31 : bit_vector;
INIT_32 : bit_vector;
INIT_33 : bit_vector;
INIT_34 : bit_vector;
INIT_35 : bit_vector;
INIT_36 : bit_vector;
INIT_37 : bit_vector;
INIT_38 : bit_vector;
INIT_39 : bit_vector;
INIT_3A : bit_vector;
INIT_3B : bit_vector;
INIT_3C : bit_vector;
INIT_3D : bit_vector;
INIT_3E : bit_vector;
INIT_3F : bit_vector;
INIT_40 : bit_vector;
INIT_41 : bit_vector;
INIT_42 : bit_vector;
INIT_43 : bit_vector;
INIT_44 : bit_vector;
INIT_45 : bit_vector;
INIT_46 : bit_vector;
INIT_47 : bit_vector;
INIT_48 : bit_vector;
INIT_49 : bit_vector;
INIT_4A : bit_vector;
INIT_4B : bit_vector;
INIT_4C : bit_vector;
INIT_4D : bit_vector;
INIT_4E : bit_vector;
INIT_4F : bit_vector;
INIT_50 : bit_vector;
INIT_51 : bit_vector;
INIT_52 : bit_vector;
INIT_53 : bit_vector;
INIT_54 : bit_vector;
INIT_55 : bit_vector;
INIT_56 : bit_vector;
INIT_57 : bit_vector;
INIT_58 : bit_vector;
INIT_59 : bit_vector;
INIT_5A : bit_vector;
INIT_5B : bit_vector;
INIT_5C : bit_vector;
INIT_5D : bit_vector;
INIT_5E : bit_vector;
INIT_5F : bit_vector;
INIT_60 : bit_vector;
INIT_61 : bit_vector;
INIT_62 : bit_vector;
INIT_63 : bit_vector;
INIT_64 : bit_vector;
INIT_65 : bit_vector;
INIT_66 : bit_vector;
INIT_67 : bit_vector;
INIT_68 : bit_vector;
INIT_69 : bit_vector;
INIT_6A : bit_vector;
INIT_6B : bit_vector;
INIT_6C : bit_vector;
INIT_6D : bit_vector;
INIT_6E : bit_vector;
INIT_6F : bit_vector;
INIT_70 : bit_vector;
INIT_71 : bit_vector;
INIT_72 : bit_vector;
INIT_73 : bit_vector;
INIT_74 : bit_vector;
INIT_75 : bit_vector;
INIT_76 : bit_vector;
INIT_77 : bit_vector;
INIT_78 : bit_vector;
INIT_79 : bit_vector;
INIT_7A : bit_vector;
INIT_7B : bit_vector;
INIT_7C : bit_vector;
INIT_7D : bit_vector;
INIT_7E : bit_vector;
INIT_7F : bit_vector;
INITP_00 : bit_vector;
INITP_01 : bit_vector;
INITP_02 : bit_vector;
INITP_03 : bit_vector;
INITP_04 : bit_vector;
INITP_05 : bit_vector;
INITP_06 : bit_vector;
INITP_07 : bit_vector;
INITP_08 : bit_vector;
INITP_09 : bit_vector;
INITP_0A : bit_vector;
INITP_0B : bit_vector;
INITP_0C : bit_vector;
INITP_0D : bit_vector;
INITP_0E : bit_vector;
INITP_0F : bit_vector
);
port (
DOA : out std_logic_vector;
DOB : out std_logic_vector;
ADDRA : in std_logic_vector;
ADDRB : in std_logic_vector;
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector;
DIB : in std_logic_vector;
ENA : in std_ulogic;
ENB : in std_ulogic;
REGCEA : in std_ulogic;
REGCEB : in std_ulogic;
RSTA : in std_ulogic;
RSTB : in std_ulogic;
WEA : in std_logic_vector;
WEB : in std_logic_vector
);
end component;
end package vcomponents;

256
rel/src/vhdl/ibm/std_ulogic_ao_support.vhdl
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138
rel/src/vhdl/ibm/std_ulogic_function_support.vhdl
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@ -77,7 +77,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- Synopsys translate_off
attribute btr_name of gate : function is "AND" ;
attribute recursive_synthesis of gate : function is 1 ;
attribute recursive_synthesis of gate : function is true ;
attribute pin_bit_information of gate : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_SCALAR"),
@ -90,7 +90,7 @@ package std_ulogic_function_support is
return std_ulogic ;
-- Synopsys translate_off
attribute btr_name of dot_and : function is "VHDL-DOTA" ;
attribute recursive_synthesis of dot_and : function is 1 ;
attribute recursive_synthesis of dot_and : function is true ;
attribute pin_bit_information of dot_and : function is
(1 => (" ","IN ","SAME","PIN_BIT_SCALAR"),
2 => (" ","OUT ","SAME","PIN_BIT_SCALAR"));
@ -101,7 +101,7 @@ package std_ulogic_function_support is
return std_ulogic ;
-- synopsys translate_off
attribute btr_name of dot_or : function is "VHDL-DOTO" ;
attribute recursive_synthesis of dot_or : function is 1 ;
attribute recursive_synthesis of dot_or : function is true ;
attribute pin_bit_information of dot_or : function is
(1 => (" ","IN ","SAME","PIN_BIT_SCALAR"),
2 => (" ","OUT ","SAME","PIN_BIT_SCALAR"));
@ -116,7 +116,7 @@ package std_ulogic_function_support is
return bit ;
-- Synopsys translate_off
attribute btr_name of clock_tree_dot : function is "VHDL-CDOT" ;
attribute recursive_synthesis of clock_tree_dot : function is 1 ;
attribute recursive_synthesis of clock_tree_dot : function is true ;
attribute pin_bit_information of clock_tree_dot : function is
(1 => (" ","IN ","SAME","PIN_BIT_SCALAR"),
2 => (" ","OUT ","SAME","PIN_BIT_SCALAR"));
@ -140,7 +140,7 @@ package std_ulogic_function_support is
);
-- synopsys translate_off
attribute btr_name of terminator : procedure is "TERMINATOR";
attribute recursive_synthesis of terminator : procedure is 1 ;
attribute recursive_synthesis of terminator : procedure is true ;
attribute pin_bit_information of terminator : procedure is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","PASS "," "," "),
@ -167,7 +167,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of delay : function is "IDENT" ;
attribute recursive_synthesis of delay : function is 1 ;
attribute recursive_synthesis of delay : function is true ;
attribute block_data of delay : function is
"SUB_FUNC=/DELAY/LOGIC_STYLE=/DIRECT/" ;
attribute pin_bit_information of delay : function is
@ -197,7 +197,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of buff : function is "IDENT" ;
attribute recursive_synthesis of buff : function is 1 ;
attribute recursive_synthesis of buff : function is true ;
attribute block_data of buff : function is
"LOGIC_STYLE=/DIRECT/" ;
attribute pin_bit_information of buff : function is
@ -227,7 +227,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of invert : function is "NOT" ;
attribute recursive_synthesis of invert : function is 1 ;
attribute recursive_synthesis of invert : function is true ;
attribute pin_bit_information of invert : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","PASS "," "," "),
@ -257,7 +257,7 @@ package std_ulogic_function_support is
return std_ulogic ;
-- synopsys translate_off
attribute btr_name of compare : function is "VHDL-COMPARE" ;
attribute recursive_synthesis of compare : function is 1 ;
attribute recursive_synthesis of compare : function is true ;
attribute pin_bit_information of compare : function is
(1 => (" ","A0 ","INCR","PIN_BIT_SCALAR"),
2 => (" ","M0 ","INCR","PIN_BIT_SCALAR"),
@ -278,7 +278,7 @@ package std_ulogic_function_support is
return std_ulogic ;
-- synopsys translate_off
attribute btr_name of parity : function is "XOR" ;
attribute recursive_synthesis of parity : function is 1 ;
attribute recursive_synthesis of parity : function is true ;
attribute pin_bit_information of parity : function is
(1 => (" ","IN ","SAME","PIN_BIT_SCALAR"),
2 => (" ","PASS "," "," "),
@ -296,7 +296,7 @@ package std_ulogic_function_support is
-- synopsys translate_off
attribute btr_name of parity_map : function is "XOR" ;
attribute recursive_synthesis of parity_map : function is 1 ;
attribute recursive_synthesis of parity_map : function is true ;
attribute block_data of parity_map : function is
"LOGIC_STYLE=/DIRECT/" ;
attribute pin_bit_information of parity_map : function is
@ -318,7 +318,7 @@ package std_ulogic_function_support is
-- synopsys translate_off
attribute btr_name of parity_gen_odd : function is "XNOR" ;
attribute recursive_synthesis of parity_gen_odd : function is 1;
attribute recursive_synthesis of parity_gen_odd : function is true;
attribute pin_bit_information of parity_gen_odd : function is
(1 => (" ","IN ","SAME","PIN_BIT_SCALAR"),
2 => (" ","PASS "," "," "),
@ -336,7 +336,7 @@ package std_ulogic_function_support is
return std_ulogic ;
-- Synopsys translate_off
attribute btr_name of parity_gen_even : function is "XOR" ;
attribute recursive_synthesis of parity_gen_even : function is 1;
attribute recursive_synthesis of parity_gen_even : function is true;
attribute pin_bit_information of parity_gen_even : function is
(1 => (" ","IN ","SAME","PIN_BIT_SCALAR"),
2 => (" ","PASS "," "," "),
@ -354,7 +354,7 @@ package std_ulogic_function_support is
return std_ulogic ;
-- Synopsys translate_off
attribute btr_name of is_parity_odd : function is "XOR" ;
attribute recursive_synthesis of is_parity_odd : function is 1;
attribute recursive_synthesis of is_parity_odd : function is true;
attribute pin_bit_information of is_parity_odd : function is
(1 => (" ","IN ","SAME","PIN_BIT_SCALAR"),
2 => (" ","PASS "," "," "),
@ -372,7 +372,7 @@ package std_ulogic_function_support is
return std_ulogic ;
-- Synopsys translate_off
attribute btr_name of is_parity_even : function is "XNOR" ;
attribute recursive_synthesis of is_parity_even : function is 1;
attribute recursive_synthesis of is_parity_even : function is true;
attribute pin_bit_information of is_parity_even : function is
(1 => (" ","IN ","SAME","PIN_BIT_SCALAR"),
2 => (" ","PASS "," "," "),
@ -405,7 +405,7 @@ package std_ulogic_function_support is
);
-- synopsys translate_off
attribute btr_name of full_add : procedure is "VHDL-FA";
attribute recursive_synthesis of full_add : procedure is 1 ;
attribute recursive_synthesis of full_add : procedure is true ;
attribute pin_bit_information of full_add : procedure is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -438,7 +438,7 @@ package std_ulogic_function_support is
return std_ulogic ;
-- synopsys translate_off
attribute btr_name of tie_0 : function is "VHDL-TIDN" ;
attribute recursive_synthesis of tie_0 : function is 1 ;
attribute recursive_synthesis of tie_0 : function is true ;
attribute block_data of tie_0 : function is
"LOGIC_STYLE=/DIRECT/" ;
attribute pin_bit_information of tie_0 : function is
@ -457,7 +457,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of vector_tie_0 : function is "VHDL-TIDN" ;
attribute recursive_synthesis of vector_tie_0 : function is 1 ;
attribute recursive_synthesis of vector_tie_0 : function is true ;
attribute block_data of vector_tie_0 : function is
"LOGIC_STYLE=/DIRECT/" ;
attribute pin_bit_information of vector_tie_0 : function is
@ -476,7 +476,7 @@ package std_ulogic_function_support is
return std_ulogic ;
-- synopsys translate_off
attribute btr_name of tie_1 : function is "VHDL-TIUP" ;
attribute recursive_synthesis of tie_1 : function is 1 ;
attribute recursive_synthesis of tie_1 : function is true ;
attribute block_data of tie_1 : function is
"LOGIC_STYLE=/DIRECT/" ;
attribute pin_bit_information of tie_1 : function is
@ -495,7 +495,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of vector_tie_1 : function is "VHDL-TIUP" ;
attribute recursive_synthesis of vector_tie_1 : function is 1 ;
attribute recursive_synthesis of vector_tie_1 : function is true ;
attribute block_data of vector_tie_1 : function is
"LOGIC_STYLE=/DIRECT/" ;
attribute pin_bit_information of vector_tie_1 : function is
@ -519,7 +519,7 @@ package std_ulogic_function_support is
return std_ulogic ;
-- synopsys translate_off
attribute btr_name of and_reduce : function is "AND" ;
attribute recursive_synthesis of and_reduce : function is 1 ;
attribute recursive_synthesis of and_reduce : function is true ;
attribute pin_bit_information of and_reduce : function is
(1 => (" ","IN ","SAME","PIN_BIT_SCALAR"),
2 => (" ","PASS "," "," "),
@ -537,7 +537,7 @@ package std_ulogic_function_support is
return std_ulogic ;
-- synopsys translate_off
attribute btr_name of or_reduce : function is "OR" ;
attribute recursive_synthesis of or_reduce : function is 1 ;
attribute recursive_synthesis of or_reduce : function is true ;
attribute pin_bit_information of or_reduce : function is
(1 => (" ","IN ","SAME","PIN_BIT_SCALAR"),
2 => (" ","PASS "," "," "),
@ -555,7 +555,7 @@ package std_ulogic_function_support is
return std_ulogic ;
-- synopsys translate_off
attribute btr_name of nand_reduce : function is "NAND" ;
attribute recursive_synthesis of nand_reduce : function is 1 ;
attribute recursive_synthesis of nand_reduce : function is true ;
attribute pin_bit_information of nand_reduce : function is
(1 => (" ","IN ","SAME","PIN_BIT_SCALAR"),
2 => (" ","PASS "," "," "),
@ -573,7 +573,7 @@ package std_ulogic_function_support is
return std_ulogic ;
-- synopsys translate_off
attribute btr_name of nor_reduce : function is "NOR" ;
attribute recursive_synthesis of nor_reduce : function is 1 ;
attribute recursive_synthesis of nor_reduce : function is true ;
attribute pin_bit_information of nor_reduce : function is
(1 => (" ","IN ","SAME","PIN_BIT_SCALAR"),
2 => (" ","PASS "," "," "),
@ -591,7 +591,7 @@ package std_ulogic_function_support is
return std_ulogic ;
-- synopsys translate_off
attribute btr_name of xor_reduce : function is "XOR" ;
attribute recursive_synthesis of xor_reduce : function is 1 ;
attribute recursive_synthesis of xor_reduce : function is true ;
attribute pin_bit_information of xor_reduce : function is
(1 => (" ","IN ","SAME","PIN_BIT_SCALAR"),
2 => (" ","PASS "," "," "),
@ -609,7 +609,7 @@ package std_ulogic_function_support is
return std_ulogic ;
-- synopsys translate_off
attribute btr_name of xnor_reduce : function is "XNOR" ;
attribute recursive_synthesis of xnor_reduce : function is 1 ;
attribute recursive_synthesis of xnor_reduce : function is true ;
attribute pin_bit_information of xnor_reduce : function is
(1 => (" ","IN ","SAME","PIN_BIT_SCALAR"),
2 => (" ","PASS "," "," "),
@ -647,7 +647,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of gate_and : function is "AND" ;
attribute recursive_synthesis of gate_and : function is 1 ;
attribute recursive_synthesis of gate_and : function is true ;
attribute pin_bit_information of gate_and : function is
(1 => (" ","IN ","SAME","PIN_BIT_SCALAR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -685,7 +685,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of gate_or : function is "OR" ;
attribute recursive_synthesis of gate_or : function is 1 ;
attribute recursive_synthesis of gate_or : function is true ;
attribute pin_bit_information of gate_or : function is
(1 => (" ","IN ","SAME","PIN_BIT_SCALAR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -723,7 +723,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of gate_nand : function is "NAND" ;
attribute recursive_synthesis of gate_nand : function is 1 ;
attribute recursive_synthesis of gate_nand : function is true ;
attribute pin_bit_information of gate_nand : function is
(1 => (" ","IN ","SAME","PIN_BIT_SCALAR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -761,7 +761,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of gate_nor : function is "NOR" ;
attribute recursive_synthesis of gate_nor : function is 1 ;
attribute recursive_synthesis of gate_nor : function is true ;
attribute pin_bit_information of gate_nor : function is
(1 => (" ","IN ","SAME","PIN_BIT_SCALAR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -790,7 +790,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of gate_xor : function is "XOR" ;
attribute recursive_synthesis of gate_xor : function is 1 ;
attribute recursive_synthesis of gate_xor : function is true ;
attribute pin_bit_information of gate_xor : function is
(1 => (" ","IN ","SAME","PIN_BIT_SCALAR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -819,7 +819,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of gate_xnor : function is "XNOR" ;
attribute recursive_synthesis of gate_xnor : function is 1 ;
attribute recursive_synthesis of gate_xnor : function is true ;
attribute pin_bit_information of gate_xnor : function is
(1 => (" ","IN ","SAME","PIN_BIT_SCALAR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -851,7 +851,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of and_2 : function is "AND" ;
attribute recursive_synthesis of and_2 : function is 1 ;
attribute recursive_synthesis of and_2 : function is true ;
attribute pin_bit_information of and_2 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -880,7 +880,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of or_2 : function is "OR" ;
attribute recursive_synthesis of or_2 : function is 1 ;
attribute recursive_synthesis of or_2 : function is true ;
attribute pin_bit_information of or_2 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -909,7 +909,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of nand_2 : function is "NAND" ;
attribute recursive_synthesis of nand_2 : function is 1 ;
attribute recursive_synthesis of nand_2 : function is true ;
attribute pin_bit_information of nand_2 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -938,7 +938,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of nor_2 : function is "NOR" ;
attribute recursive_synthesis of nor_2 : function is 1 ;
attribute recursive_synthesis of nor_2 : function is true ;
attribute pin_bit_information of nor_2 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -967,7 +967,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of xor_2 : function is "XOR" ;
attribute recursive_synthesis of xor_2 : function is 1 ;
attribute recursive_synthesis of xor_2 : function is true ;
attribute pin_bit_information of xor_2 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -996,7 +996,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of xnor_2 : function is "XNOR" ;
attribute recursive_synthesis of xnor_2 : function is 1 ;
attribute recursive_synthesis of xnor_2 : function is true ;
attribute pin_bit_information of xnor_2 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -1030,7 +1030,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of and_3 : function is "AND" ;
attribute recursive_synthesis of and_3 : function is 1 ;
attribute recursive_synthesis of and_3 : function is true ;
attribute pin_bit_information of and_3 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -1062,7 +1062,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of or_3 : function is "OR" ;
attribute recursive_synthesis of or_3 : function is 1 ;
attribute recursive_synthesis of or_3 : function is true ;
attribute pin_bit_information of or_3 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -1094,7 +1094,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of nand_3 : function is "NAND" ;
attribute recursive_synthesis of nand_3 : function is 1 ;
attribute recursive_synthesis of nand_3 : function is true ;
attribute pin_bit_information of nand_3 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -1126,7 +1126,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of nor_3 : function is "NOR" ;
attribute recursive_synthesis of nor_3 : function is 1 ;
attribute recursive_synthesis of nor_3 : function is true ;
attribute pin_bit_information of nor_3 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -1158,7 +1158,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of xor_3 : function is "XOR" ;
attribute recursive_synthesis of xor_3 : function is 1 ;
attribute recursive_synthesis of xor_3 : function is true ;
attribute pin_bit_information of xor_3 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -1190,7 +1190,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of xnor_3 : function is "XNOR" ;
attribute recursive_synthesis of xnor_3 : function is 1 ;
attribute recursive_synthesis of xnor_3 : function is true ;
attribute pin_bit_information of xnor_3 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -1226,7 +1226,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of and_4 : function is "AND" ;
attribute recursive_synthesis of and_4 : function is 1 ;
attribute recursive_synthesis of and_4 : function is true ;
attribute pin_bit_information of and_4 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -1261,7 +1261,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of or_4 : function is "OR" ;
attribute recursive_synthesis of or_4 : function is 1 ;
attribute recursive_synthesis of or_4 : function is true ;
attribute pin_bit_information of or_4 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -1296,7 +1296,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of nand_4 : function is "NAND" ;
attribute recursive_synthesis of nand_4 : function is 1 ;
attribute recursive_synthesis of nand_4 : function is true ;
attribute pin_bit_information of nand_4 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -1331,7 +1331,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of nor_4 : function is "NOR" ;
attribute recursive_synthesis of nor_4 : function is 1 ;
attribute recursive_synthesis of nor_4 : function is true ;
attribute pin_bit_information of nor_4 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -1371,7 +1371,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of and_5 : function is "AND" ;
attribute recursive_synthesis of and_5 : function is 1 ;
attribute recursive_synthesis of and_5 : function is true ;
attribute pin_bit_information of and_5 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -1409,7 +1409,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of or_5 : function is "OR" ;
attribute recursive_synthesis of or_5 : function is 1 ;
attribute recursive_synthesis of or_5 : function is true ;
attribute pin_bit_information of or_5 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -1447,7 +1447,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of nand_5 : function is "NAND" ;
attribute recursive_synthesis of nand_5 : function is 1 ;
attribute recursive_synthesis of nand_5 : function is true ;
attribute pin_bit_information of nand_5 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -1485,7 +1485,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of nor_5 : function is "NOR" ;
attribute recursive_synthesis of nor_5 : function is 1 ;
attribute recursive_synthesis of nor_5 : function is true ;
attribute pin_bit_information of nor_5 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -1527,7 +1527,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of and_6 : function is "AND" ;
attribute recursive_synthesis of and_6 : function is 1 ;
attribute recursive_synthesis of and_6 : function is true ;
attribute pin_bit_information of and_6 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -1568,7 +1568,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of or_6 : function is "OR" ;
attribute recursive_synthesis of or_6 : function is 1 ;
attribute recursive_synthesis of or_6 : function is true ;
attribute pin_bit_information of or_6 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -1609,7 +1609,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of nand_6 : function is "NAND" ;
attribute recursive_synthesis of nand_6 : function is 1 ;
attribute recursive_synthesis of nand_6 : function is true ;
attribute pin_bit_information of nand_6 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -1650,7 +1650,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of nor_6 : function is "NOR" ;
attribute recursive_synthesis of nor_6 : function is 1 ;
attribute recursive_synthesis of nor_6 : function is true ;
attribute pin_bit_information of nor_6 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -1696,7 +1696,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of and_7 : function is "AND" ;
attribute recursive_synthesis of and_7 : function is 1 ;
attribute recursive_synthesis of and_7 : function is true ;
attribute pin_bit_information of and_7 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -1740,7 +1740,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of or_7 : function is "OR" ;
attribute recursive_synthesis of or_7 : function is 1 ;
attribute recursive_synthesis of or_7 : function is true ;
attribute pin_bit_information of or_7 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -1784,7 +1784,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of nand_7 : function is "NAND" ;
attribute recursive_synthesis of nand_7 : function is 1 ;
attribute recursive_synthesis of nand_7 : function is true ;
attribute pin_bit_information of nand_7 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -1828,7 +1828,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of nor_7 : function is "NOR" ;
attribute recursive_synthesis of nor_7 : function is 1 ;
attribute recursive_synthesis of nor_7 : function is true ;
attribute pin_bit_information of nor_7 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -1877,7 +1877,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of and_8 : function is "AND" ;
attribute recursive_synthesis of and_8 : function is 1 ;
attribute recursive_synthesis of and_8 : function is true ;
attribute pin_bit_information of and_8 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -1924,7 +1924,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of or_8 : function is "OR" ;
attribute recursive_synthesis of or_8 : function is 1 ;
attribute recursive_synthesis of or_8 : function is true ;
attribute pin_bit_information of or_8 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -1971,7 +1971,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of nand_8 : function is "NAND" ;
attribute recursive_synthesis of nand_8 : function is 1 ;
attribute recursive_synthesis of nand_8 : function is true ;
attribute pin_bit_information of nand_8 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -2018,7 +2018,7 @@ package std_ulogic_function_support is
return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of nor_8 : function is "NOR" ;
attribute recursive_synthesis of nor_8 : function is 1 ;
attribute recursive_synthesis of nor_8 : function is true ;
attribute pin_bit_information of nor_8 : function is
(1 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
2 => (" ","IN ","SAME","PIN_BIT_VECTOR"),
@ -2048,7 +2048,7 @@ package std_ulogic_function_support is
return std_return_4 ;
-- synopsys translate_off
attribute btr_name of decode_2to4 : function is "VHDL-DECODE";
attribute recursive_synthesis of decode_2to4 : function is 1 ;
attribute recursive_synthesis of decode_2to4 : function is true ;
attribute pin_bit_information of decode_2to4 : function is
(1 => (" ","D1 ","DECR","PIN_BIT_SCALAR"),
2 => (" ","PASS "," "," "),
@ -2066,7 +2066,7 @@ package std_ulogic_function_support is
return std_return_8 ;
-- synopsys translate_off
attribute btr_name of decode_3to8 : function is "VHDL-DECODE";
attribute recursive_synthesis of decode_3to8 : function is 1 ;
attribute recursive_synthesis of decode_3to8 : function is true ;
attribute pin_bit_information of decode_3to8 : function is
(1 => (" ","D2 ","DECR","PIN_BIT_SCALAR"),
2 => (" ","PASS "," "," "),
@ -2084,7 +2084,7 @@ package std_ulogic_function_support is
return std_return_16 ;
-- synopsys translate_off
attribute btr_name of decode_4to16 : function is "VHDL-DECODE";
attribute recursive_synthesis of decode_4to16 : function is 1 ;
attribute recursive_synthesis of decode_4to16 : function is true ;
attribute pin_bit_information of decode_4to16 : function is
(1 => (" ","D3 ","DECR","PIN_BIT_SCALAR"),
2 => (" ","PASS "," "," "),
@ -2102,7 +2102,7 @@ package std_ulogic_function_support is
return std_return_32 ;
-- synopsys translate_off
attribute btr_name of decode_5to32 : function is "VHDL-DECODE";
attribute recursive_synthesis of decode_5to32 : function is 1 ;
attribute recursive_synthesis of decode_5to32 : function is true ;
attribute pin_bit_information of decode_5to32 : function is
(1 => (" ","D4 ","DECR","PIN_BIT_SCALAR"),
2 => (" ","PASS "," "," "),
@ -2120,7 +2120,7 @@ package std_ulogic_function_support is
return std_return_64 ;
-- synopsys translate_off
attribute btr_name of decode_6to64 : function is "VHDL-DECODE";
attribute recursive_synthesis of decode_6to64 : function is 1 ;
attribute recursive_synthesis of decode_6to64 : function is true ;
attribute pin_bit_information of decode_6to64 : function is
(1 => (" ","D5 ","DECR","PIN_BIT_SCALAR"),
2 => (" ","PASS "," "," "),

28
rel/src/vhdl/ibm/std_ulogic_mux_support.vhdl
View File

@ -44,7 +44,7 @@ package std_ulogic_mux_support is
) return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of mux_2to1 : function is "VHDL-MUX" ;
attribute recursive_synthesis of mux_2to1 : function is 1;
attribute recursive_synthesis of mux_2to1 : function is true;
attribute pin_bit_information of mux_2to1 : function is
(1 => (" ","S0 ","DECR","PIN_BIT_SCALAR"),
2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"),
@ -79,7 +79,7 @@ package std_ulogic_mux_support is
) return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of mux_4to1 : function is "VHDL-MUX" ;
attribute recursive_synthesis of mux_4to1 : function is 1;
attribute recursive_synthesis of mux_4to1 : function is true;
attribute pin_bit_information of mux_4to1 : function is
(1 => (" ","S1 ","DECR","PIN_BIT_SCALAR"),
2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"),
@ -124,7 +124,7 @@ package std_ulogic_mux_support is
) return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of mux_8to1 : function is "VHDL-MUX" ;
attribute recursive_synthesis of mux_8to1 : function is 1;
attribute recursive_synthesis of mux_8to1 : function is true;
attribute pin_bit_information of mux_8to1 : function is
(1 => (" ","S2 ","DECR","PIN_BIT_SCALAR"),
2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"),
@ -161,7 +161,7 @@ package std_ulogic_mux_support is
) return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of not_mux_2to1 : function is "VHDL-MUX" ;
attribute recursive_synthesis of not_mux_2to1 : function is 1;
attribute recursive_synthesis of not_mux_2to1 : function is true;
attribute pin_bit_information of not_mux_2to1 : function is
(1 => (" ","S0 ","DECR","PIN_BIT_SCALAR"),
2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"),
@ -196,7 +196,7 @@ package std_ulogic_mux_support is
) return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of not_mux_4to1 : function is "VHDL-MUX" ;
attribute recursive_synthesis of not_mux_4to1 : function is 1;
attribute recursive_synthesis of not_mux_4to1 : function is true;
attribute pin_bit_information of not_mux_4to1 : function is
(1 => (" ","S1 ","DECR","PIN_BIT_SCALAR"),
2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"),
@ -241,7 +241,7 @@ package std_ulogic_mux_support is
) return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of not_mux_8to1 : function is "VHDL-MUX" ;
attribute recursive_synthesis of not_mux_8to1 : function is 1;
attribute recursive_synthesis of not_mux_8to1 : function is true;
attribute pin_bit_information of not_mux_8to1 : function is
(1 => (" ","S2 ","DECR","PIN_BIT_SCALAR"),
2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"),
@ -281,7 +281,7 @@ package std_ulogic_mux_support is
) return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of select_1of2 : function is "VHDL-SELECT" ;
attribute recursive_synthesis of select_1of2 : function is 1;
attribute recursive_synthesis of select_1of2 : function is true;
attribute pin_bit_information of select_1of2 : function is
(1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"),
2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"),
@ -319,7 +319,7 @@ package std_ulogic_mux_support is
) return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of select_1of3 : function is "VHDL-SELECT" ;
attribute recursive_synthesis of select_1of3 : function is 1;
attribute recursive_synthesis of select_1of3 : function is true;
attribute pin_bit_information of select_1of3 : function is
(1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"),
2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"),
@ -363,7 +363,7 @@ package std_ulogic_mux_support is
) return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of select_1of4 : function is "VHDL-SELECT" ;
attribute recursive_synthesis of select_1of4 : function is 1;
attribute recursive_synthesis of select_1of4 : function is true;
attribute pin_bit_information of select_1of4 : function is
(1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"),
2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"),
@ -425,7 +425,7 @@ package std_ulogic_mux_support is
) return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of select_1of8 : function is "VHDL-SELECT" ;
attribute recursive_synthesis of select_1of8 : function is 1;
attribute recursive_synthesis of select_1of8 : function is true;
attribute pin_bit_information of select_1of8 : function is
(1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"),
2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"),
@ -471,7 +471,7 @@ package std_ulogic_mux_support is
) return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of not_select_1of2 : function is "VHDL-SELECT" ;
attribute recursive_synthesis of not_select_1of2 : function is 1;
attribute recursive_synthesis of not_select_1of2 : function is true;
attribute pin_bit_information of not_select_1of2 : function is
(1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"),
2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"),
@ -509,7 +509,7 @@ package std_ulogic_mux_support is
) return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of not_select_1of3 : function is "VHDL-SELECT" ;
attribute recursive_synthesis of not_select_1of3 : function is 1;
attribute recursive_synthesis of not_select_1of3 : function is true;
attribute PIN_BIT_INFORMATION of not_select_1of3 : function is
(1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"),
2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"),
@ -553,7 +553,7 @@ package std_ulogic_mux_support is
) return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of not_select_1of4 : function is "VHDL-SELECT" ;
attribute recursive_synthesis of not_select_1of4 : function is 1;
attribute recursive_synthesis of not_select_1of4 : function is true;
attribute pin_bit_information of not_select_1of4 : function is
(1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"),
2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"),
@ -615,7 +615,7 @@ package std_ulogic_mux_support is
) return std_ulogic_vector ;
-- synopsys translate_off
attribute btr_name of not_select_1of8 : function is "VHDL-SELECT" ;
attribute recursive_synthesis of not_select_1of8 : function is 1;
attribute recursive_synthesis of not_select_1of8 : function is true;
attribute pin_bit_information of not_select_1of8 : function is
(1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"),
2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"),

3
rel/src/vhdl/tri/ramb16_s18_s18.vhdl
View File

@ -15,9 +15,6 @@ library ibm;
use ibm.std_ulogic_support.all;
use ibm.std_ulogic_function_support.all;
library UNISIM;
use UNISIM.vcomponents.all;
library UNIMACRO;
use UNIMACRO.vcomponents.all;

3
rel/src/vhdl/tri/ramb16_s36_s36.vhdl
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@ -15,9 +15,6 @@ library ibm;
use ibm.std_ulogic_support.all;
use ibm.std_ulogic_function_support.all;
library UNISIM;
use UNISIM.vcomponents.all;
library UNIMACRO;
use UNIMACRO.vcomponents.all;

3
rel/src/vhdl/tri/ramb16_s9_s9.vhdl
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@ -15,9 +15,6 @@ library ibm;
use ibm.std_ulogic_support.all;
use ibm.std_ulogic_function_support.all;
library UNISIM;
use UNISIM.vcomponents.all;
library UNIMACRO;
use UNIMACRO.vcomponents.all;

1
rel/src/vhdl/tri/tri_boltreg_p.vhdl
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@ -17,7 +17,6 @@
library ieee; use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ibm;
library support;
use support.power_logic_pkg.all;
library tri; use tri.tri_latches_pkg.all;

2
rel/src/vhdl/tri/tri_ser_rlmreg_p.vhdl
View File

@ -7,7 +7,7 @@
-- This README will be updated with additional information when OpenPOWER's
-- license is available.
library ieee,ibm,support,tri;
library ieee,support,tri;
use ieee.std_logic_1164.all;
use support.power_logic_pkg.all;
use tri.tri_latches_pkg.all;

2
rel/src/vhdl/work/pcq_abist_bolton_stg.vhdl
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@ -14,7 +14,7 @@
library ieee;
use ieee.std_logic_1164.all;
library ibm,clib;
library ibm;
use ibm.std_ulogic_support.all;
use ibm.std_ulogic_function_support.all;
library support;

2
rel/src/vhdl/work/pcq_regs_fir.vhdl
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@ -14,7 +14,7 @@
library ieee;
use ieee.std_logic_1164.all;
library ibm,clib;
library ibm;
use ibm.std_ulogic_support.all;
use ibm.std_ulogic_function_support.all;
use ibm.std_ulogic_unsigned.all;

2
rel/src/vhdl/work/xuq_byp_cr.vhdl
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@ -9,7 +9,7 @@
-- Description: XU Bypass Unit
--
library ieee,ibm,support,tri,clib,work;
library ieee,ibm,support,tri,work;
use ieee.std_logic_1164.all;
use ibm.std_ulogic_function_support.all;
use tri.tri_latches_pkg.all;

2
rel/src/vhdl/work/xuq_debug_mux32.vhdl
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@ -9,7 +9,7 @@
-- Description: LSU Debug Event Muxing
--
library ieee,ibm,support,work,tri,clib,work;
library ieee,ibm,support,work,tri,work;
use ieee.std_logic_1164.all;
use support.power_logic_pkg.all;
use ibm.std_ulogic_support.all;

1
rel/src/vhdl/work/xuq_dec_dcdmrg.vhdl
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@ -18,7 +18,6 @@ LIBRARY ibm;
LIBRARY support;
USE support.power_logic_pkg.all;
LIBRARY tri; USE tri.tri_latches_pkg.all;
LIBRARY clib ;
LIBRARY work; USE work.xuq_pkg.all;
entity xuq_dec_dcdmrg is

2
rel/src/vhdl/work/xuq_fxua_data.vhdl
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@ -9,7 +9,7 @@
-- Description: XU Exception Handler
--
library ieee,ibm,support,work,tri,clib;
library ieee,ibm,support,work,tri;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use support.power_logic_pkg.all;

1
rel/src/vhdl/work/xuq_lsu_cmp_cmp31.vhdl
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@ -24,7 +24,6 @@ LIBRARY ibm;
LIBRARY support;
USE support.power_logic_pkg.all;
LIBRARY tri; USE tri.tri_latches_pkg.all;
LIBRARY clib ;
entity xuq_lsu_cmp_cmp31 is
generic( expand_type: integer := 2 ); -- 0 - ibm tech, 1 - other );

1
rel/src/vhdl/work/xuq_lsu_cmp_cmp36e.vhdl
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@ -24,7 +24,6 @@ LIBRARY ibm;
LIBRARY support;
USE support.power_logic_pkg.all;
LIBRARY tri; USE tri.tri_latches_pkg.all;
LIBRARY clib ;
entity xuq_lsu_cmp_cmp36e is
generic( expand_type: integer := 2 ); -- 0 - ibm tech, 1 - other );

1
rel/src/vhdl/work/xuq_lsu_data_rot32_ru.vhdl
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@ -19,7 +19,6 @@ LIBRARY ibm;
LIBRARY support;
USE support.power_logic_pkg.all;
LIBRARY tri; USE tri.tri_latches_pkg.all;
LIBRARY clib ;
-- ##########################################################################################
-- VHDL Contents

1
rel/src/vhdl/work/xuq_lsu_data_rot32s_ru.vhdl
View File

@ -20,7 +20,6 @@ LIBRARY ibm;
LIBRARY support;
USE support.power_logic_pkg.all;
LIBRARY tri; USE tri.tri_latches_pkg.all;
LIBRARY clib ;
-- ##########################################################################################
-- VHDL Contents

2
rel/src/vhdl/work/xuq_lsu_debug.vhdl
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@ -9,7 +9,7 @@
-- Description: LSU Debug Event Muxing
--
library ieee,ibm,support,work,tri,clib;
library ieee,ibm,support,work,tri;
use ieee.std_logic_1164.all;
use support.power_logic_pkg.all;
use tri.tri_latches_pkg.all;

2
rel/src/vhdl/work/xuq_pkg.vhdl
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@ -9,7 +9,7 @@
-- Description: XU Package
--
library ieee,ibm;
library ieee;
use ieee.std_logic_1164.all;
package xuq_pkg is

24
run.py Normal file
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@ -0,0 +1,24 @@
#!/usr/bin/env python3
"""VUnit run script."""
from pathlib import Path
from vunit import VUnit
prj = VUnit.from_argv()
_rel = Path(__file__).parent / "rel"
library_names = ["support", "ibm", "clib", "tri"]
for library_name in library_names:
prj.add_library(library_name).add_source_files(
_rel / f"src/vhdl/{library_name}/*.vhdl"
)
# VUnit doesn't accept libraries named work. These files are compiled to the top library
prj.add_library("top").add_source_files(_rel / "src/vhdl/work/*.vhdl")
# Simulation only library containing VHDL mocks for Verilog UNIMACROs
prj.add_library("unimacro").add_source_files(_rel / "sim/unimacro/*.vhdl")
prj.main()