openpower-cores.a2i

mirror of https://github.com/openpower-cores/a2i.git synced 2026-01-13 07:19:50 +00:00

History

Lars Asplund fee9c135cc Added VHDL mocks for used UNIMACROs.

These mocks allow for a pure VHDL CI environment. The mocks are currently empty and provide no functionality. This is acceptable as long as no testbenches depend on them.
For now their primary purpose is to allow the project to be compiled by GHDL.

Some files also reference the UNISIM library. These references are not used and have been removed.

2021-03-13 22:54:24 +01:00

build

add comments

2020-08-27 11:22:43 -04:00

doc

Create a2_run_video.md

2020-09-14 19:22:31 -05:00

fpga

create

2020-06-28 18:40:39 -04:00

sim/unimacro

Added VHDL mocks for used UNIMACROs.

2021-03-13 22:54:24 +01:00

src/vhdl

Added VHDL mocks for used UNIMACROs.

2021-03-13 22:54:24 +01:00

readme.md

create

2020-06-28 18:40:39 -04:00

readme.md

Directory Structure

src/vhdl
   clib (low-level components)
   ibm (std_ulogic)
   support (power_logic subtype)
   tri (latches and arrays)
   work (macros)

build
   a2x (project)
   ip_cache (empty until project built)
   ip_repo (empty until IP built/copied)
   ip_user (IP macros to be built)
   tcl (build scripts)
   xdc (constraints)

fpga
   tcl

doc
   core user guide, etc.

Build Process

IP

IP is created in ip_user and copied to ip_repo for use in top level bd.

See build/ip_user/xxx/readme.md.

Core:

a2x_axi

Simple card components:

a2x_axi_reg 
a2x_dbug
a2x_reset

Help Vivado attach to VIO correctly:

reverserator_3
reverserator_4
reverserator_32
reverserator_64

Project

See build/a2x/readme.md.

create project
synth/implement