mirror of
https://github.com/openpower-cores/a2i.git
synced 2026-01-13 07:19:50 +00:00
fee9c135cc
These mocks allow for a pure VHDL CI environment. The mocks are currently empty and provide no functionality. This is acceptable as long as no testbenches depend on them. For now their primary purpose is to allow the project to be compiled by GHDL. Some files also reference the UNISIM library. These references are not used and have been removed.
188 lines
6.9 KiB
VHDL
188 lines
6.9 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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package vcomponents is
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component BRAM_TDP_MACRO
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generic (
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BRAM_SIZE : string;
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DEVICE : string;
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DOA_REG : integer;
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DOB_REG : integer;
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INIT_A : bit_vector;
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INIT_B : bit_vector;
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INIT_FILE : string;
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READ_WIDTH_A : integer;
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READ_WIDTH_B : integer;
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SIM_COLLISION_CHECK : string;
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SRVAL_A : bit_vector;
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SRVAL_B : bit_vector;
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WRITE_MODE_A : string;
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WRITE_MODE_B : string;
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WRITE_WIDTH_A : integer;
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WRITE_WIDTH_B : integer;
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INIT_00 : bit_vector;
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INIT_01 : bit_vector;
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INIT_02 : bit_vector;
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INIT_03 : bit_vector;
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INIT_04 : bit_vector;
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INIT_05 : bit_vector;
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INIT_06 : bit_vector;
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INIT_07 : bit_vector;
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INIT_08 : bit_vector;
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INIT_09 : bit_vector;
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INIT_0A : bit_vector;
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INIT_0B : bit_vector;
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INIT_0C : bit_vector;
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INIT_0D : bit_vector;
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INIT_0E : bit_vector;
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INIT_0F : bit_vector;
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INIT_10 : bit_vector;
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INIT_11 : bit_vector;
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INIT_12 : bit_vector;
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INIT_13 : bit_vector;
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INIT_14 : bit_vector;
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INIT_15 : bit_vector;
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INIT_16 : bit_vector;
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INIT_17 : bit_vector;
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INIT_18 : bit_vector;
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INIT_19 : bit_vector;
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INIT_1A : bit_vector;
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INIT_1B : bit_vector;
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INIT_1C : bit_vector;
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INIT_1D : bit_vector;
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INIT_1E : bit_vector;
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INIT_1F : bit_vector;
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INIT_20 : bit_vector;
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INIT_21 : bit_vector;
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INIT_22 : bit_vector;
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INIT_23 : bit_vector;
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INIT_24 : bit_vector;
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INIT_25 : bit_vector;
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INIT_26 : bit_vector;
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INIT_27 : bit_vector;
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INIT_28 : bit_vector;
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INIT_29 : bit_vector;
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INIT_2A : bit_vector;
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INIT_2B : bit_vector;
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INIT_2C : bit_vector;
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INIT_2D : bit_vector;
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INIT_2E : bit_vector;
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INIT_2F : bit_vector;
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INIT_30 : bit_vector;
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INIT_31 : bit_vector;
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INIT_32 : bit_vector;
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INIT_33 : bit_vector;
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INIT_34 : bit_vector;
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INIT_35 : bit_vector;
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INIT_36 : bit_vector;
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INIT_37 : bit_vector;
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INIT_38 : bit_vector;
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INIT_39 : bit_vector;
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INIT_3A : bit_vector;
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INIT_3B : bit_vector;
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INIT_3C : bit_vector;
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INIT_3D : bit_vector;
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INIT_3E : bit_vector;
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INIT_3F : bit_vector;
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INIT_40 : bit_vector;
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INIT_41 : bit_vector;
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INIT_42 : bit_vector;
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INIT_43 : bit_vector;
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INIT_44 : bit_vector;
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INIT_45 : bit_vector;
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INIT_46 : bit_vector;
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INIT_47 : bit_vector;
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INIT_48 : bit_vector;
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INIT_49 : bit_vector;
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INIT_4A : bit_vector;
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INIT_4B : bit_vector;
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INIT_4C : bit_vector;
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INIT_4D : bit_vector;
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INIT_4E : bit_vector;
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INIT_4F : bit_vector;
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INIT_50 : bit_vector;
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INIT_51 : bit_vector;
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INIT_52 : bit_vector;
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INIT_53 : bit_vector;
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INIT_54 : bit_vector;
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INIT_55 : bit_vector;
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INIT_56 : bit_vector;
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INIT_57 : bit_vector;
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INIT_58 : bit_vector;
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INIT_59 : bit_vector;
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INIT_5A : bit_vector;
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INIT_5B : bit_vector;
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INIT_5C : bit_vector;
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INIT_5D : bit_vector;
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INIT_5E : bit_vector;
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INIT_5F : bit_vector;
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INIT_60 : bit_vector;
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INIT_61 : bit_vector;
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INIT_62 : bit_vector;
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INIT_63 : bit_vector;
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INIT_64 : bit_vector;
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INIT_65 : bit_vector;
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INIT_66 : bit_vector;
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INIT_67 : bit_vector;
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INIT_68 : bit_vector;
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INIT_69 : bit_vector;
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INIT_6A : bit_vector;
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INIT_6B : bit_vector;
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INIT_6C : bit_vector;
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INIT_6D : bit_vector;
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INIT_6E : bit_vector;
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INIT_6F : bit_vector;
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INIT_70 : bit_vector;
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INIT_71 : bit_vector;
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INIT_72 : bit_vector;
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INIT_73 : bit_vector;
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INIT_74 : bit_vector;
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INIT_75 : bit_vector;
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INIT_76 : bit_vector;
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INIT_77 : bit_vector;
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INIT_78 : bit_vector;
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INIT_79 : bit_vector;
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INIT_7A : bit_vector;
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INIT_7B : bit_vector;
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INIT_7C : bit_vector;
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INIT_7D : bit_vector;
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INIT_7E : bit_vector;
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INIT_7F : bit_vector;
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INITP_00 : bit_vector;
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INITP_01 : bit_vector;
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INITP_02 : bit_vector;
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INITP_03 : bit_vector;
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INITP_04 : bit_vector;
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INITP_05 : bit_vector;
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INITP_06 : bit_vector;
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INITP_07 : bit_vector;
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INITP_08 : bit_vector;
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INITP_09 : bit_vector;
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INITP_0A : bit_vector;
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INITP_0B : bit_vector;
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INITP_0C : bit_vector;
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INITP_0D : bit_vector;
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INITP_0E : bit_vector;
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INITP_0F : bit_vector
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);
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port (
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DOA : out std_logic_vector;
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DOB : out std_logic_vector;
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ADDRA : in std_logic_vector;
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ADDRB : in std_logic_vector;
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CLKA : in std_ulogic;
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CLKB : in std_ulogic;
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DIA : in std_logic_vector;
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DIB : in std_logic_vector;
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ENA : in std_ulogic;
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ENB : in std_ulogic;
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REGCEA : in std_ulogic;
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REGCEB : in std_ulogic;
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RSTA : in std_ulogic;
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RSTB : in std_ulogic;
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WEA : in std_logic_vector;
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WEB : in std_logic_vector
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);
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end component;
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end package vcomponents;
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