17 Commits

This Branch

This Branch

All Branches

Author	SHA1	Message	Date
OpenPower Cores	397bed8ce3	Update README.md	2022-04-05 18:13:26 -05:00
Bill Flynn	edee22506b	Update README.md	2022-04-05 18:08:39 -05:00
Bill Flynn	18af29ac8b	Merge pull request #13 from antonblanchard/sv-reserved ... Avoid SystemVerilog reserved words	2021-08-29 15:33:05 -05:00
wtf	32174bf011	license change	2021-07-26 19:32:23 -04:00
Anton Blanchard	ac4063ab73	Avoid SystemVerilog reserved words ... Yosys doesn't like bit and byte being used as identifiers.	2021-03-13 09:18:14 +11:00
openpowerwtf	07e252685a	Merge pull request #2 from openpowerwtf/master ... iucr0 init with bp enabled	2020-09-16 20:31:58 -05:00
wtf	fc356ae8e2	iucr0 init with bp enabled	2020-09-16 21:29:16 -04:00
OpenPower Cores	87a8d1866f	added Paul's updates for source comments	2020-09-16 12:32:12 -05:00
wtf	b9ebec3ab9	fix syntax	2020-09-16 12:41:36 -04:00
wtf	ed6a17f4f9	add work comments	2020-09-16 12:04:16 -04:00
wtf	59c5f83dd4	remove dup header	2020-09-16 11:50:24 -04:00
wtf	d2f2e855b7	add trilib comments	2020-09-16 11:49:41 -04:00
OpenPower Cores	80d426bd2f	Merge pull request #1 from shingarov/fix-linguist ... Stop GitHub from reporting "74.6% Coq"	2020-09-16 09:24:32 -05:00
Boris Shingarov	6dfa6d756c	Stop GitHub from reporting "74.6% Coq"	2020-09-15 19:29:11 -04:00
OpenPower Cores	080f86a3fb	Create a2_build_video.md	2020-09-14 19:52:57 -05:00
OpenPower Cores	189bdc03bb	Delete empty	2020-09-14 19:47:17 -05:00
wtf	dc16f9b5a5	initial	2020-09-14 08:57:56 -04:00