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Commit Processor module WIP as of 2012-07-06: Branch Return, Exit,
Return, Return Special, Variable Field Isolate.
This commit is contained in:
paul
@@ -7,8 +7,10 @@
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*
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* Instance variables in all caps generally refer to register or flip-flop (FF)
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* entities in the processor hardware. See the Burroughs B5500 Reference Manual
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* (1021326, May 1967) for details.
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* (1021326, May 1967) and B5281 Processor Training Manual (B5281.55, August 1966)
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* for details:
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* http://bitsavers.org/pdf/burroughs/B5000_5500_5700/1021326_B5500_RefMan_May67.pdf
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* http://bitsavers.org/pdf/burroughs/B5000_5500_5700/B5281.55_ProcessorTrainingManual_Aug66.pdf
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*
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* B5500 word format: 48 bits plus (hidden) parity.
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* Bit 0 is high-order, bit 47 is low-order, big-endian character ordering.
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@@ -675,6 +677,22 @@ B5500Processor.prototype.indexDescriptor = function() {
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return interrupted;
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};
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/**************************************/
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B5500Processor.prototype.presenceTest(word) {
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/* Tests and returns the presence bit [2:1] of the "word" parameter. If
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0, the p-bit interrupt is set; otherwise no further action */
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if (word % 0x400000000000 >= 0x200000000000) {
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return 1;
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} else {
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if (this.NCSF) {
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this.I = (this.I & 0x0F) | 0x70; // set I05/6/7: p-bit
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cc.signalInterrupt();
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}
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return 0;
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}
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};
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/**************************************/
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B5500Processor.prototype.buildMSCW = function() {
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/* Return a Mark Stack Control Word from current processor state */
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@@ -686,6 +704,23 @@ B5500Processor.prototype.buildMSCW = function() {
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0xC00000000000;
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};
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/**************************************/
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B5500Processor.prototype.applyMSCW = function(word) {
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/* Set processor state from fields of the Mark Stack Control
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Word in the "word" parameter */
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var f;
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f = word % 0x8000; // [33:15]
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word = (word-f)/0x8000;
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this.F = f = word % 0x8000; // [18:15]
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word = (word-f)/0x8000;
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this.SALF = f = word % 2; // [17:1]
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word = (word-f)/0x02;
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this.MSFF = word % 0x02; // [16:1]
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word = (word - word%0x04)/0x04;
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this.R = word % 0x200; // [6:9]
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};
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/**************************************/
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B5500Processor.prototype.buildRCW = function(descriptorCall) {
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/* Return a Return Control Word from the current processor state */
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@@ -700,6 +735,29 @@ B5500Processor.prototype.buildRCW = function(descriptorCall) {
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(descriptorCall ? 0xE00000000000 : 0xC00000000000);
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};
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/**************************************/
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B5500Processor.prototype.applyRCW = function(word) {
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/* Set processor state from fields of the Return Control Word in
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the "word" parameter. Returns the state of the OPDC/DESC bit [2:1] */
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var f;
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this.C = f = word % 0x8000; // [33:15]
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word = (word-f)/0x8000;
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this.F = f = word % 0x8000; // [18:15]
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word = (word-f)/0x8000;
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this.K = f = word % 0x08; // [15:3]
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word = (word-f)/0x08;
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this.G = f = word % 0x08; // [12:3]
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word = (word-f)/0x08;
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this.L = f = word % 0x04; // [10:2]
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word = (word-f)/0x04;
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this.V = f = word % 0x08; // [7:3]
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word = (word-f)/0x08;
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this.H = word % 0x08; // [4:3]
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word = (word - word % 0x10)/0x10;
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return word % 0x02; // [2:1]
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};
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/**************************************/
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B5500Processor.prototype.enterCharModeInline() {
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/* Implements the 4441=CMN syllable */
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@@ -732,7 +790,7 @@ B5500Processor.prototype.enterCharModeInline() {
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this.K = (bw % 0x40000) >>> 15;
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} else { // B contains a descriptor
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if (bw % 0x400000000000 < 0x200000000000) { // it's an absent descriptor
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this.I = (this.I & 0x0F) | 0xE0; // set I06/7/8: p-bit
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this.I = (this.I & 0x0F) | 0x70; // set I05/6/7: p-bit
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cc.signalInterrupt(); // NOTE: docs do not mention if this is inhibited in control state
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} else {
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this.S = bw % 0x8000;
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@@ -740,7 +798,6 @@ B5500Processor.prototype.enterCharModeInline() {
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}
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};
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/**************************************/
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B5500Processor.prototype.enterSubroutine = function(descriptorCall) {
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/* Enters a subroutine via the present program descriptor in A as part
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@@ -791,6 +848,51 @@ B5500Processor.prototype.enterSubroutine = function(descriptorCall) {
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}
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};
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/**************************************/
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B5500Processor.prototype.exitSubroutine = function() {
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/* Exits a subroutine by restoring the processor state from RCW and MSCW words
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in the stack. The RCW is assumed to be in the B register, pointing to the MSCW.
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The A register is not affected by this routine. If SALF & MSFF bits in the MSCW
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are set, link back through the MSCWs until one is found that has either bit not
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set, and store that MSCW at [R]+7. This is the last prior MSCW that actually
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points to a RCW, thus skipping over any pending subroutine calls that are still
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building their parameters in the stack. Returns results as follows:
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0 = entered by OPDC
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1 = entered by DESC
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2 = flag bit interrupt set, terminate operator
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*/
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var result;
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if (this.B < 0x800000000000) { // flag bit not set
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result = 2;
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if (this.NCSF) {
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this.I = (this.I & 0x0F) | 0x80; // set I08: flag-bit
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cc.signalInterrupt();
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}
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} else { // flag bit is set
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result = this.applyRCW(this.B);
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this.X = this.B % 0x8000000000; // save F setting from MSCW to restore S at end
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this.access(0x30); // P = [C], C set from RCW
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this.S = this.F;
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this.access(0x03); // B = [S], fetch the MSCW
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this.applyMSCW(this.B);
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if (this.MSFF && this.SALF) {
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this.Q |= 0x20; // set Q06F, not used except for display
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do {
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this.S = (this.B % 0x40000000) >>> 15;
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this.access(0x03); // B = [S], fetch prior MSCW
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} while (((this.B - this.B % 0x40000000)/0x40000000) % 0x04 == 3); // MSFF & SALF
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this.S = (this.R*64) + 7;
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this.access(0x0B); // [S] = B, store last MSCW at [R]+7
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}
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this.S = ((this.X % 0x40000000) >>> 15) - 1;
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this.BROF = 0;
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}
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return result;
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};
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/**************************************/
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B5500Processor.prototype.operandCall = function() {
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/* OPDC, the moral equivalent of "load accumulator" on lesser
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@@ -831,7 +933,7 @@ B5500Processor.prototype.operandCall = function() {
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case 5:
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// Absent data or program descriptor
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if (this.NCSF) {
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this.I = (this.I & 0x0F) | 0xE0; // set I06/7/8: p-bit
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this.I = (this.I & 0x0F) | 0x70; // set I05/6/7: p-bit
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cc.signalInterrupt();
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// else if control state, we're done
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}
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@@ -885,7 +987,7 @@ B5500Processor.prototype.descriptorCall = function() {
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case 5:
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// Absent data or program descriptor
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if (this.NCSF) {
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this.I = (this.I & 0x0F) | 0xE0; // set I06/7/8: p-bit
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this.I = (this.I & 0x0F) | 0x70; // set I05/6/7: p-bit
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cc.signalInterrupt();
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// else if control state, we're done
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}
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@@ -1293,7 +1395,7 @@ B5500Processor.prototype.run = function() {
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this.AROF == 1;
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break;
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case 0x02: // 0215: LOR=logical OR
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case 0x02: // 0215: LOR=logical OR
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// assert(this.AROF == 1 && this.BROF == 1);
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flagBit = cc.bit(this.B, 0); // save B flag bit
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aHi = this.A / w32;
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@@ -1387,7 +1489,7 @@ B5500Processor.prototype.run = function() {
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// TODO: should this be excluding the flag bit in the comparison?
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this.B = (this.A != this.B) ? 1 : 0;
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this.AROF = 0;
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this.BROF = 1;
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this.BROF = 1;
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break;
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case 0x08: // 1025: XCH=exchange TOS words
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@@ -1460,7 +1562,7 @@ B5500Processor.prototype.run = function() {
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this.A = cc.fieldInsert(this.A, 1, 1, 0);
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} else {
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this.A = cc.fieldInsert(this.A, 1, 1, 1);
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}
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}
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this.AROF = 1;
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break;
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@@ -1526,15 +1628,57 @@ B5500Processor.prototype.run = function() {
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case 0x1D: // XX35: exit & return ops
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switch (variant) {
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case 0x01: // 0135: BRT=branch return
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adjustAEmpty();
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if (!this.BROF) {
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this.Q |= 0x04; // Q03F: not used, except for display purposes
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adjustBFull();
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}
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if (this.presenceTest(this.B)) {
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this.S = (this.B % 0x40000000) >>> 15;
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this.C = this.B % 0x8000;
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this.access(0x30); // P = [C]
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this.L = 0;
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this.access(0x03); // B = [S], fetch MSCW
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this.S--;
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this.applyMSCW(this.B);
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this.BROF = 0;
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}
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break;
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case 0x02: // 0235: RTN=return normal
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this.adjustAFull();
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this.S = this.F;
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this.access(0x03); // B = [S], fetch the RCW
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switch (this.exitSubroutine()) {
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case 0:
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this.X = 0;
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operandCall();
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case 1:
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this.Q |= 0x10; // set Q05F, for display only
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this.X = 0;
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descriptorCall();
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}
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break;
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case 0x04: // 0435: XIT=exit procedure
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this.AROF = 0;
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this.S = this.F;
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this.access(0x03); // B = [S], fetch the RCW
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this.exitSubroutine();
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break;
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case 0x0A: // 1235: RTS=return special
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this.adjustAFull();
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this.access(0x03); // B = [S], fetch the RCW
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switch (this.exitSubroutine()) {
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case 0:
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this.X = 0;
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operandCall();
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case 1:
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this.Q |= 0x10; // set Q05F, for display only
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this.X = 0;
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descriptorCall();
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}
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break;
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}
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break;
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@@ -1589,6 +1733,23 @@ B5500Processor.prototype.run = function() {
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break;
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case 0x25: // XX45: ISO=Variable Field Isolate op
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this.adjustAFull();
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t2 = variant >>> 3; // number of whole chars
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if (t2) {
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t1 = this.G*6 + this.H; // starting source bit position
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t2 = t2*6 - (variant & 7); // number of bits
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if (t1+t2 <= 48) {
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this.A = cc.fieldIsolate(this.A, t1, t2);
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} else { // handle wrap-around in the source value
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this.A = cc.fieldInsert(
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cc.fieldIsolate(this.A, 96-t1-t2, t1+t2-48), 48-t2, 48-t1,
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cc.fieldIsolate(this.A, 0, 48-t1));
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}
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// approximate the shift cycle counts
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this.cycleCount += (variant >>> 3) + (variant & 7) + this.G + this.H;
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this.G = (this.G + variant >>> 3) & 7;
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this.H = 0;
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}
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break;
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case 0x29: // XX51: delete & conditional branch ops
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@@ -1637,11 +1798,11 @@ B5500Processor.prototype.run = function() {
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case 0x35: // XX65: TRB=Transfer Bits
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this.adjustABFull();
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t1 = this.G*8 + this.H; // A register starting bit nr
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t1 = this.G*6 + this.H; // A register starting bit nr
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if (t1+variant > 48) {
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variant = 48-t1;
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}
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t2 = this.K*8 + this.V; // B register starting bit nr
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t2 = this.K*6 + this.V; // B register starting bit nr
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if (t2+variant > 48) {
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variant = 48-t2;
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}
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@@ -1654,11 +1815,11 @@ B5500Processor.prototype.run = function() {
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case 0x39: // XX71: FCL=Compare Field Low
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this.adjustABFull();
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t1 = this.G*8 + this.H; // A register starting bit nr
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t1 = this.G*6 + this.H; // A register starting bit nr
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if (t1+variant > 48) {
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variant = 48-t1;
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}
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t2 = this.K*8 + this.V; // B register starting bit nr
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t2 = this.K*6 + this.V; // B register starting bit nr
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if (t2+variant > 48) {
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variant = 48-t2;
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}
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@@ -1672,11 +1833,11 @@ B5500Processor.prototype.run = function() {
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case 0x3D: // XX75: FCE=Compare Field Equal
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this.adjustABFull();
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t1 = this.G*8 + this.H; // A register starting bit nr
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t1 = this.G*6 + this.H; // A register starting bit nr
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if (t1+variant > 48) {
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variant = 48-t1;
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}
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t2 = this.K*8 + this.V; // B register starting bit nr
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t2 = this.K*6 + this.V; // B register starting bit nr
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if (t2+variant > 48) {
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variant = 48-t2;
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}
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