mirror of
https://github.com/prirun/p50em.git
synced 2026-02-26 16:23:28 +00:00
jump directly to shift to eliminate a sub-switch (Primos rebuild gcov)
After profiling Primos rebuild, shift instructions are #8
This commit is contained in:
Jim
57
dispatch.h
57
dispatch.h
@@ -355,10 +355,63 @@ DIGEN(001306, "MDRS", d_mdxx);
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DIGEN(001307, "MDWC", d_mdxx);
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DIGEN(001324, "MDIW", d_mdxx);
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/* initialize class 1 generics (shift group) */
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/* initialize entire class 1 generics (shift group) to "badshift",
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then initialize each individual shift instruction */
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for (i = 02000; i < 04000; i++) {
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disp_gen[i] = &&d_gen1;
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disp_gen[i] = &&d_badshift;
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}
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for (i = 02000; i < 02100; i++) {
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disp_gen[i] = &&d_lrl;
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}
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for (i = 02100; i < 02200; i++) {
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disp_gen[i] = &&d_lrs;
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}
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for (i = 02200; i < 02300; i++) {
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disp_gen[i] = &&d_lrr;
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}
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for (i = 02300; i < 02400; i++) {
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disp_gen[i] = &&d_300shift;
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}
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for (i = 02400; i < 02500; i++) {
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disp_gen[i] = &&d_arl;
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}
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for (i = 02500; i < 02600; i++) {
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disp_gen[i] = &&d_ars;
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}
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for (i = 02600; i < 02700; i++) {
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disp_gen[i] = &&d_arr;
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}
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for (i = 03000; i < 03100; i++) {
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disp_gen[i] = &&d_lll;
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}
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for (i = 03100; i < 03200; i++) {
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disp_gen[i] = &&d_lls;
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}
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for (i = 03200; i < 03300; i++) {
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disp_gen[i] = &&d_llr;
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}
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for (i = 03400; i < 03500; i++) {
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disp_gen[i] = &&d_all;
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}
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for (i = 03500; i < 03600; i++) {
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disp_gen[i] = &&d_als;
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}
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for (i = 03600; i < 03700; i++) {
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disp_gen[i] = &&d_alr;
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}
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/* initialize class 2 generics (skip group) */
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2
ea64v.h
2
ea64v.h
@@ -32,7 +32,7 @@ static inline ea_t ea64v (unsigned short inst, ea_t earp) {
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ea_s = rph;
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/* first check for long, 2-word, V-mode memory references. About
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75% of V-mode references are in this form */
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half of V-mode references are in this form */
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if ((inst & 01740) == 01400) {
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a = iget16(RP);
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348
em.c
348
em.c
@@ -3774,11 +3774,22 @@ static inline arfa(int n, int val) {
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TRACE(T_FLOW, " after add, FAR=%o/%o, FLR=%o\n", crsl[FAR0+2*n]>>16, crsl[FAR0+2*n]&0xFFFF, crsl[FLR0+2*n]);
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}
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/* inline function to extract shift count from an instruction */
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static inline unsigned short shiftcount (inst) {
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unsigned short scount;
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scount = -inst & 077;
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if (scount == 0)
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scount = 0100;
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return scount;
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}
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/* 32-bit shifts */
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static inline unsigned int lrs(unsigned int val, short scount) {
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static inline unsigned int lrs(unsigned int val, unsigned short inst) {
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unsigned short scount;
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scount = shiftcount(inst);
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if (scount <= 32) {
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EXPCL(val & (((unsigned int)0x80000000) >> (32-scount)));
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return (*(int *)&val) >> scount;
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@@ -3790,9 +3801,11 @@ static inline unsigned int lrs(unsigned int val, short scount) {
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return 0;
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}
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static inline unsigned int lls(unsigned int val, short scount) {
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static inline unsigned int lls(unsigned int val, unsigned short inst) {
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unsigned short scount;
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int templ;
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scount = shiftcount(inst);
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if (scount < 32) {
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templ = 0x80000000;
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templ = templ >> scount; /* create mask */
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@@ -3806,8 +3819,10 @@ static inline unsigned int lls(unsigned int val, short scount) {
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}
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}
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static inline unsigned int lll(unsigned int val, short scount) {
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static inline unsigned int lll(unsigned int val, unsigned short inst) {
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unsigned short scount;
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scount = shiftcount(inst);
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if (scount <= 32) {
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EXPCL(val & (((unsigned int)0x80000000) >> (scount-1)));
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return val << scount;
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@@ -3816,8 +3831,10 @@ static inline unsigned int lll(unsigned int val, short scount) {
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return 0;
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}
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static inline unsigned int lrl(unsigned int val, short scount) {
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static inline unsigned int lrl(unsigned int val, unsigned short inst) {
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unsigned short scount;
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scount = shiftcount(inst);
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if (scount <= 32) {
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EXPCL(val & (((unsigned int)0x80000000) >> (32-scount)));
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return val >> scount;
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@@ -3828,8 +3845,10 @@ static inline unsigned int lrl(unsigned int val, short scount) {
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/* 16-bit shifts */
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static inline unsigned short arl (unsigned short val, short scount) {
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static inline unsigned short arl (unsigned short val, unsigned short inst) {
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unsigned short scount;
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scount = shiftcount(inst);
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if (scount <= 16) {
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EXPCL(val & (((unsigned short)0x8000) >> (16-scount)));
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return val >> scount;
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@@ -3839,8 +3858,10 @@ static inline unsigned short arl (unsigned short val, short scount) {
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}
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}
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static inline unsigned short all (unsigned short val, short scount) {
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static inline unsigned short all (unsigned short val, unsigned short inst) {
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unsigned short scount;
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scount = shiftcount(inst);
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if (scount <= 16) {
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EXPCL(val & (((unsigned short)0x8000) >> (scount-1)));
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return val << scount;
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@@ -3850,10 +3871,11 @@ static inline unsigned short all (unsigned short val, short scount) {
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}
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}
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static inline unsigned short als (unsigned short val, short scount) {
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static inline unsigned short als (unsigned short val, unsigned short inst) {
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unsigned short scount;
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short tempa;
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scount = shiftcount(inst);
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if (scount <= 15) {
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tempa = 0100000;
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tempa = tempa >> scount; /* create mask */
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@@ -3866,8 +3888,10 @@ static inline unsigned short als (unsigned short val, short scount) {
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return 0;
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}
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static inline unsigned short ars (unsigned short val, short scount) {
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static inline unsigned short ars (unsigned short val, unsigned short inst) {
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unsigned short scount;
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scount = shiftcount(inst);
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if (scount <= 16) {
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EXPCL(val & (((unsigned short)0x8000) >> (16-scount)));
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return (*(short *)&val) >> scount;
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@@ -3881,15 +3905,19 @@ static inline unsigned short ars (unsigned short val, short scount) {
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/* 32-bit rotates */
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static inline unsigned int lrr(unsigned int val, short scount) {
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static inline unsigned int lrr(unsigned int val, unsigned short inst) {
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unsigned short scount;
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scount = shiftcount(inst);
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scount = ((scount-1)%32)+1; /* make scount 1-32 */
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EXPCL(val & (((unsigned int)0x80000000) >> (32-scount)));
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return (val >> scount) | (val << (32-scount));
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}
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static inline unsigned int llr(unsigned int val, short scount) {
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static inline unsigned int llr(unsigned int val, unsigned short inst) {
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unsigned short scount;
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scount = shiftcount(inst);
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scount = ((scount-1)%32)+1; /* make scount 1-32 */
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EXPCL(val & (((unsigned int)0x80000000) >> (scount-1)));
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return (val << scount) | (val >> (32-scount));
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@@ -3897,15 +3925,19 @@ static inline unsigned int llr(unsigned int val, short scount) {
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/* 16-bit rotates */
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static inline unsigned int alr(unsigned short val, short scount) {
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static inline unsigned int alr(unsigned short val, unsigned short inst) {
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unsigned short scount;
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scount = shiftcount(inst);
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scount = ((scount-1)%16)+1; /* make scount 1-16 */
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EXPCL(val & (((unsigned short)0x8000) >> (scount-1)));
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return (val << scount) | (val >> (16-scount));
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}
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static inline unsigned int arr(unsigned short val, short scount) {
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static inline unsigned int arr(unsigned short val, unsigned short inst) {
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unsigned short scount;
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scount = shiftcount(inst);
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scount = ((scount-1)%16)+1; /* make scount 1-16 */
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EXPCL(val & (((unsigned short)0x8000) >> (16-scount)));
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return (val >> scount) | (val << (16-scount));
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@@ -6924,7 +6956,6 @@ d_mdxx: /* 01304-01307, 01324 */
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TRACE(T_FLOW, " MDxx\n");
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goto fetch;
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d_gen1:
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/* this is a bit weird here: the shift group is really only for
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V-mode instructions, but Prime put some I-mode generics in
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@@ -6933,144 +6964,138 @@ d_gen1:
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something like LRL executed in I-mode, but the emulator will
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just do it. */
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//TRACE(T_INST, " shift group\n");
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scount = -inst & 077;
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if (scount == 0)
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scount = 0100;
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switch (inst & 01700) {
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d_lrl: /* 00000 - LRL */
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TRACE(T_FLOW, " LRL %d\n", shiftcount(inst));
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crsl[GR2] = lrl(crsl[GR2], inst);
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goto fetch;
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case 00000: /* LRL */
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TRACE(T_FLOW, " LRL %d\n", scount);
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crsl[GR2] = lrl(crsl[GR2], scount);
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break;
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case 00100: /* LRS (different in R & V modes) */
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TRACE(T_FLOW, " LRS %d\n", scount);
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if (crs[KEYS] & 010000) { /* V/I mode */
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crsl[GR2] = lrs(crsl[GR2], scount);
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d_lrs: /* 00100 - LRS (different in R & V modes) */
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TRACE(T_FLOW, " LRS %d\n", shiftcount(inst));
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if (crs[KEYS] & 010000) { /* V/I mode */
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crsl[GR2] = lrs(crsl[GR2], inst);
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} else {
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scount = shiftcount(inst);
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utempa = crs[B] & 0x8000; /* save B bit 1 */
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if (scount <= 31) {
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templ = (crs[A]<<16) | ((crs[B] & 0x7FFF)<<1);
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EXPCL(templ & BITMASK32(32-scount));
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templ = templ >> (scount+1);
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crs[A] = templ >> 15;
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crs[B] = (templ & 0x7FFF) | utempa;
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} else if (crs[A] & 0x8000) {
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*(int *)(crs+A) = 0xFFFF7FFF | utempa;
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SETCL;
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} else {
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utempa = crs[B] & 0x8000; /* save B bit 1 */
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if (scount <= 31) {
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templ = (crs[A]<<16) | ((crs[B] & 0x7FFF)<<1);
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EXPCL(templ & BITMASK32(32-scount));
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templ = templ >> (scount+1);
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crs[A] = templ >> 15;
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crs[B] = (templ & 0x7FFF) | utempa;
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} else if (crs[A] & 0x8000) {
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*(int *)(crs+A) = 0xFFFF7FFF | utempa;
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SETCL;
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} else {
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CLEARCL;
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*(int *)(crs+A) = utempa;
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}
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CLEARCL;
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*(int *)(crs+A) = utempa;
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}
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break;
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case 00200: /* LRR */
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TRACE(T_FLOW, " LRR %d\n", scount);
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crsl[GR2] = lrr(crsl[GR2], scount);
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break;
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case 00300:
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switch (inst) {
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case 0040310: /* SSSN */
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sssn();
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break;
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case 0040300: /* DRN */
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case 0040301: /* DRNP */
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case 0040302: /* DRNZ */
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case 0040303: /* FRNP */
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case 0040320: /* FRNM */
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case 0040321: /* FRNZ */
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TRACE(T_FLOW, " DRNx/FRNx(V) UII\n");
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fault(UIIFAULT, RPL, RP);
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break;
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default:
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goto badshift;
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}
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break;
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|
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case 00400: /* ARL */
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TRACE(T_FLOW, " ARL %d\n", scount);
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crs[A] = arl(crs[A], scount);
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break;
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|
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case 00500: /* ARS */
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TRACE(T_FLOW, " ARS %d\n", scount);
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crs[A] = ars(crs[A], scount);
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break;
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|
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case 00600: /* ARR */
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TRACE(T_FLOW, " ARR %d\n", scount);
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crs[A] = arr(crs[A], scount);
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break;
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case 01000: /* LLL */
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TRACE(T_FLOW, " LLL %d\n", scount);
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crsl[GR2] = lll(crsl[GR2], scount);
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break;
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|
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case 01100: /* LLS (different in R/V modes) */
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TRACE(T_FLOW, " LLS %d\n", scount);
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if (crs[KEYS] & 010000) /* V/I mode */
|
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crsl[GR2] = lls(crsl[GR2], scount);
|
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else {
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utempa = crs[B] & 0x8000; /* save B bit 1 */
|
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if (scount < 31) {
|
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utempl = (crs[A]<<16) | ((crs[B] & 0x7FFF)<<1);
|
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templ2 = 0x80000000;
|
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templ2 = templ2 >> scount; /* create mask */
|
||||
templ2 = templ2 & utempl; /* grab bits */
|
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templ2 = templ2 >> (31-scount); /* sign extend them */
|
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EXPCL(!(templ2 == -1 || templ2 == 0));
|
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//printf(" before: A=%x, B=%x, utempl=%x, ", crs[A], crs[B], utempl);
|
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utempl = utempl << scount;
|
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crs[A] = utempl >> 16;
|
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crs[B] = ((utempl >> 1) & 0x7FFF) | utempa;
|
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//printf(" after: A=%x, B=%x, utempl=%x\n", crs[A], crs[B], utempl);
|
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} else {
|
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EXPCL(*(unsigned int *)(crs+A) != 0);
|
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*(unsigned int *)(crs+A) = utempa;
|
||||
}
|
||||
}
|
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if ((crs[KEYS] & 0100400) == 0100400)
|
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mathexception('i', FC_INT_OFLOW, 0);
|
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break;
|
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|
||||
case 01200: /* LLR */
|
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TRACE(T_FLOW, " LLR %d\n", scount);
|
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crsl[GR2] = llr(crsl[GR2], scount);
|
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break;
|
||||
|
||||
case 01400: /* ALL */
|
||||
TRACE(T_FLOW, " ALL %d\n", scount);
|
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crs[A] = all(crs[A], scount);
|
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break;
|
||||
|
||||
case 01500: /* ALS */
|
||||
TRACE(T_FLOW, " ALS %d\n", scount);
|
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crs[A] = als(crs[A], scount);
|
||||
if ((crs[KEYS] & 0100400) == 0100400)
|
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mathexception('i', FC_INT_OFLOW, 0);
|
||||
break;
|
||||
|
||||
case 01600: /* ALR */
|
||||
TRACE(T_FLOW, " ALR %d\n", scount);
|
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crs[A] = alr(crs[A], scount);
|
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break;
|
||||
|
||||
default:
|
||||
badshift:
|
||||
printf("emulator warning: unrecognized class 1 (shift) generic instruction %06o at %o/%o\n", inst, RPH, RPL);
|
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TRACE(T_FLOW, " unrecognized shift instruction!: %o\n", inst);
|
||||
}
|
||||
goto fetch;
|
||||
|
||||
/* class 2 generic instructions (skip group) */
|
||||
d_lrr: /* 00200 - LRR */
|
||||
TRACE(T_FLOW, " LRR %d\n", shiftcount(inst));
|
||||
crsl[GR2] = lrr(crsl[GR2], inst);
|
||||
goto fetch;
|
||||
|
||||
d_300shift: /* 00300 - generic extension */
|
||||
switch (inst) {
|
||||
|
||||
case 0040310: /* SSSN */
|
||||
sssn();
|
||||
break;
|
||||
|
||||
case 0040300: /* DRN */
|
||||
case 0040301: /* DRNP */
|
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case 0040302: /* DRNZ */
|
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case 0040303: /* FRNP */
|
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case 0040320: /* FRNM */
|
||||
case 0040321: /* FRNZ */
|
||||
TRACE(T_FLOW, " DRNx/FRNx(V) UII\n");
|
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fault(UIIFAULT, RPL, RP);
|
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break;
|
||||
|
||||
default:
|
||||
goto d_badshift;
|
||||
}
|
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goto fetch;
|
||||
|
||||
d_arl: /* 00400 - ARL */
|
||||
TRACE(T_FLOW, " ARL %d\n", shiftcount(inst));
|
||||
crs[A] = arl(crs[A], inst);
|
||||
goto fetch;
|
||||
|
||||
d_ars: /* 00500 - ARS */
|
||||
TRACE(T_FLOW, " ARS %d\n", shiftcount(inst));
|
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crs[A] = ars(crs[A], inst);
|
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goto fetch;
|
||||
|
||||
d_arr: /* 00600 - ARR */
|
||||
TRACE(T_FLOW, " ARR %d\n", shiftcount(inst));
|
||||
crs[A] = arr(crs[A], inst);
|
||||
goto fetch;
|
||||
|
||||
d_lll: /* 01000 - LLL */
|
||||
TRACE(T_FLOW, " LLL %d\n", shiftcount(inst));
|
||||
crsl[GR2] = lll(crsl[GR2], inst);
|
||||
goto fetch;
|
||||
|
||||
d_lls: /* 01100 - LLS (different in R/V modes) */
|
||||
TRACE(T_FLOW, " LLS %d\n", shiftcount(inst));
|
||||
if (crs[KEYS] & 010000) /* V/I mode */
|
||||
crsl[GR2] = lls(crsl[GR2], inst);
|
||||
else {
|
||||
scount = shiftcount(inst);
|
||||
utempa = crs[B] & 0x8000; /* save B bit 1 */
|
||||
if (scount < 31) {
|
||||
utempl = (crs[A]<<16) | ((crs[B] & 0x7FFF)<<1);
|
||||
templ2 = 0x80000000;
|
||||
templ2 = templ2 >> scount; /* create mask */
|
||||
templ2 = templ2 & utempl; /* grab bits */
|
||||
templ2 = templ2 >> (31-scount); /* sign extend them */
|
||||
EXPCL(!(templ2 == -1 || templ2 == 0));
|
||||
//printf(" before: A=%x, B=%x, utempl=%x, ", crs[A], crs[B], utempl);
|
||||
utempl = utempl << scount;
|
||||
crs[A] = utempl >> 16;
|
||||
crs[B] = ((utempl >> 1) & 0x7FFF) | utempa;
|
||||
//printf(" after: A=%x, B=%x, utempl=%x\n", crs[A], crs[B], utempl);
|
||||
} else {
|
||||
EXPCL(*(unsigned int *)(crs+A) != 0);
|
||||
*(unsigned int *)(crs+A) = utempa;
|
||||
}
|
||||
}
|
||||
if ((crs[KEYS] & 0100400) == 0100400)
|
||||
mathexception('i', FC_INT_OFLOW, 0);
|
||||
goto fetch;
|
||||
|
||||
d_llr: /* 01200 - LLR */
|
||||
TRACE(T_FLOW, " LLR %d\n", shiftcount(inst));
|
||||
crsl[GR2] = llr(crsl[GR2], inst);
|
||||
goto fetch;
|
||||
|
||||
d_all: /* 01400 - ALL */
|
||||
TRACE(T_FLOW, " ALL %d\n", shiftcount(inst));
|
||||
crs[A] = all(crs[A], inst);
|
||||
goto fetch;
|
||||
|
||||
d_als: /* 01500 - ALS */
|
||||
TRACE(T_FLOW, " ALS %d\n", shiftcount(inst));
|
||||
crs[A] = als(crs[A], inst);
|
||||
if ((crs[KEYS] & 0100400) == 0100400)
|
||||
mathexception('i', FC_INT_OFLOW, 0);
|
||||
goto fetch;
|
||||
|
||||
d_alr: /* 01600 - ALR */
|
||||
TRACE(T_FLOW, " ALR %d\n", shiftcount(inst));
|
||||
crs[A] = alr(crs[A], inst);
|
||||
goto fetch;
|
||||
|
||||
d_badshift:
|
||||
printf("emulator warning: unrecognized class 1 (shift) generic instruction %06o at %o/%o\n", inst, RPH, RPL);
|
||||
TRACE(T_FLOW, " unrecognized shift instruction!: %o\n", inst);
|
||||
goto fetch;
|
||||
|
||||
|
||||
/* class 2 generic instructions (skip group) */
|
||||
|
||||
d_nopskp: /* 0101000 */
|
||||
TRACE(T_FLOW, " NOP-SKP\n");
|
||||
@@ -8116,21 +8141,18 @@ imode:
|
||||
|
||||
case 005:
|
||||
TRACE(T_FLOW, " SHL\n");
|
||||
scount = -ea & 077;
|
||||
if (scount == 0)
|
||||
scount = 0100;
|
||||
switch ((ea >> 14) & 3) {
|
||||
case 0:
|
||||
crsl[dr] = lll(crsl[dr], scount);
|
||||
crsl[dr] = lll(crsl[dr], ea);
|
||||
break;
|
||||
case 1:
|
||||
crs[dr*2] = all(crs[dr*2], scount);
|
||||
crs[dr*2] = all(crs[dr*2], ea);
|
||||
break;
|
||||
case 2:
|
||||
crsl[dr] = lrl(crsl[dr], scount);
|
||||
crsl[dr] = lrl(crsl[dr], ea);
|
||||
break;
|
||||
case 3:
|
||||
crs[dr*2] = arl(crs[dr*2], scount);
|
||||
crs[dr*2] = arl(crs[dr*2], ea);
|
||||
break;
|
||||
default:
|
||||
warn("I-mode SHL switch?");
|
||||
@@ -8234,25 +8256,22 @@ imode:
|
||||
|
||||
case 015:
|
||||
TRACE(T_FLOW, " SHA\n");
|
||||
scount = -ea & 077;
|
||||
if (scount == 0)
|
||||
scount = 0100;
|
||||
switch ((ea >> 14) & 3) {
|
||||
case 0:
|
||||
crsl[dr] = lls(crsl[dr], scount);
|
||||
crsl[dr] = lls(crsl[dr], ea);
|
||||
if ((crs[KEYS] & 0100400) == 0100400)
|
||||
mathexception('i', FC_INT_OFLOW, 0);
|
||||
break;
|
||||
case 1:
|
||||
crs[dr*2] = als(crs[dr*2], scount);
|
||||
crs[dr*2] = als(crs[dr*2], ea);
|
||||
if ((crs[KEYS] & 0100400) == 0100400)
|
||||
mathexception('i', FC_INT_OFLOW, 0);
|
||||
break;
|
||||
case 2:
|
||||
crsl[dr] = lrs(crsl[dr], scount);
|
||||
crsl[dr] = lrs(crsl[dr], ea);
|
||||
break;
|
||||
case 3:
|
||||
crs[dr*2] = ars(crs[dr*2], scount);
|
||||
crs[dr*2] = ars(crs[dr*2], ea);
|
||||
break;
|
||||
default:
|
||||
fatal("SHA?");
|
||||
@@ -8380,21 +8399,18 @@ imode:
|
||||
|
||||
case 024:
|
||||
TRACE(T_FLOW, " ROT\n");
|
||||
scount = -ea & 077;
|
||||
if (scount == 0)
|
||||
scount = 0100;
|
||||
switch ((ea >> 14) & 3) {
|
||||
case 0:
|
||||
crsl[dr] = llr(crsl[dr], scount);
|
||||
crsl[dr] = llr(crsl[dr], ea);
|
||||
break;
|
||||
case 1:
|
||||
crs[dr*2] = alr(crs[dr*2], scount);
|
||||
crs[dr*2] = alr(crs[dr*2], ea);
|
||||
break;
|
||||
case 2:
|
||||
crsl[dr] = lrr(crsl[dr], scount);
|
||||
crsl[dr] = lrr(crsl[dr], ea);
|
||||
break;
|
||||
case 3:
|
||||
crs[dr*2] = arr(crs[dr*2], scount);
|
||||
crs[dr*2] = arr(crs[dr*2], ea);
|
||||
break;
|
||||
default:
|
||||
warn("I-mode ROT switch?");
|
||||
|
||||
Reference in New Issue
Block a user