mirror of
https://github.com/prirun/p50em.git
synced 2026-03-03 17:56:27 +00:00
add access bits to brp.vpn entries, use brp cache for put16 & put32
added get32m & put32m: these always map changed get32 and put32 to be inlined changed mem[] references to MEM[] to allow experiments tried using register for MEM pointer - not so great tried using register for instcount - screwed up (very sluggish)
This commit is contained in:
Jim
@@ -111,13 +111,13 @@ MRGEN(03503, "JSX", d_jsx);
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#define GENIX(inst) ((inst>>4) & 06000) | (inst & 01777)
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#define DIGEN(opcode, name, target) \
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gvp->disp_gen[GENIX(opcode)] = &⌖ \
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disp_gen[GENIX(opcode)] = &⌖ \
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//printf("Opcode %06o (%s), ix=%0o\n", opcode, name, GENIX(opcode))
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/* initialize entire table to jump to bad generic label */
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for (i=0; i < 010000; i++) {
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gvp->disp_gen[i] = &&d_badgen;
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disp_gen[i] = &&d_badgen;
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}
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/* initialize class 0 generics (first 2 bits are zero) */
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@@ -230,14 +230,14 @@ DIGEN(001324, "MDIW", d_mdxx);
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/* initialize class 1 generics (shift group) */
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for (i = 02000; i < 04000; i++) {
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gvp->disp_gen[i] = &&d_gen1;
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disp_gen[i] = &&d_gen1;
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}
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/* initialize class 2 generics (skip group) */
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#if 0
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for (i = 04000; i < 06000; i++) {
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gvp->disp_gen[i] = &&d_gen2;
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disp_gen[i] = &&d_gen2;
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}
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#endif
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282
em.c
282
em.c
@@ -379,7 +379,7 @@ typedef struct {
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} iotlbe_t;
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/* the emulator uses a special, very small address translation cache
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to hold the virtual page address and corresponding mem[] pointer
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to hold the virtual page address and corresponding MEM[] pointer
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for a few special pages:
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- the current instruction page (RPBR)
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@@ -419,11 +419,23 @@ typedef struct {
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#define UNBR 6
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#define BRP_SIZE 7
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/* NOTE: vpn is a segment number/word offset Prime virtual address
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corresponding to the physical page of memory in memp. The high-
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order fault bit of vpn is never set. The ring and extension bits
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are used to store the 3-bit access field from the STLB for the
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current ring (remember that all brp entries are invalidated by
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PCL and PRTN when the ring might change).
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Storing the access bits in the vpn allows use of of the brp
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supercache for write accesses as well as read accesses. */
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typedef struct {
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unsigned short *memp; /* mem[] physical page address */
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unsigned short *memp; /* MEM[] physical page address */
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ea_t vpn; /* corresponding virtual page address */
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} brp_t;
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void *disp_gen[4096]; /* generic dispatch table */
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/* "gv" is a static structure used to hold "hot" global variables. These
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are pointed to by a dedicated register, so that the usual PowerPC global
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variable instructions aren't needed: these variables can be directly
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@@ -431,24 +443,7 @@ typedef struct {
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typedef struct {
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void *disp_gen[4096]; /* generic dispatch table */
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void *disp_mr[128]; /* V/R memory ref dispatch table */
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/* traceflags is the variable used to test tracing of each instruction
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traceuser is the user number to trace, 0 meaning any user
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traceseg is the procedure segment number to trace, 0 meaning any
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savetraceflags hold the real traceflags, while "traceflags" switches
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on and off for each instruction
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TRACEUSER is a macro that is true if the current user is being traced
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*/
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FILE *tracefile; /* trace.log file */
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int traceflags; /* each bit is a trace flag */
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int savetraceflags;
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int traceuser; /* OWNERL to trace */
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int traceseg; /* RPH segment # to trace */
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int numtraceprocs; /* # of procedures we're tracing */
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unsigned short *physmem; /* pointer to Prime physical memory */
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int intvec; /* currently raised interrupt (if >= zero) */
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@@ -480,9 +475,29 @@ typedef struct {
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int mapvamisses; /* STLB misses */
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int supercalls; /* supercache hits */
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int supermisses;
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void *disp_mr[128]; /* V/R memory ref dispatch table */
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/* traceflags is the variable used to test tracing of each instruction
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traceuser is the user number to trace, 0 meaning any user
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traceseg is the procedure segment number to trace, 0 meaning any
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savetraceflags hold the real traceflags, while "traceflags" switches
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on and off for each instruction
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TRACEUSER is a macro that is true if the current user is being traced
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*/
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FILE *tracefile; /* trace.log file */
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int traceflags; /* each bit is a trace flag */
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int savetraceflags;
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int traceuser; /* OWNERL to trace */
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int traceseg; /* RPH segment # to trace */
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int numtraceprocs; /* # of procedures we're tracing */
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} gv_t;
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static gv_t gv;
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#if 1
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register gv_t *gvp asm ("r28");
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register brp_t *eap asm ("r27"); /* effective address brp pointer */
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@@ -508,8 +523,9 @@ static jmp_buf jmpbuf; /* for longjumps to the fetch loop */
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#define MAXMB 512
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#define MEMSIZE MAXMB/2*1024*1024
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#define MEM physmem
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static unsigned short mem[MEMSIZE]; /* system's physical memory */
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static unsigned short physmem[MEMSIZE]; /* system's physical memory */
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static int memlimit; /* user's desired memory limit (-mem) */
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#define MAKEVA(seg,word) ((((int)(seg))<<16) | (word))
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@@ -766,12 +782,10 @@ char *searchloadmap(int addr, char type) {
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0 = PCL (PACC)
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2 = read (RACC)
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3 = write (WACC) = read+write
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4 = execute (XACC)
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*/
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#define PACC 0
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#define RACC 2
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#define WACC 3
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#define XACC 4
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/* NOTE: this is the 6350 STLB hash function, giving a 9-bit index 0-511.
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@@ -835,14 +849,14 @@ static pa_t mapva(ea_t ea, ea_t rp, short intacc, unsigned short *access) {
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if (relseg >= nsegs)
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fault(SEGFAULT, 1, ea); /* fcode = segment too big */
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staddr = (dtar & 0x003F0000) | ((dtar & 0x7FFF)<<1);
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sdw = *(unsigned int *)(mem+staddr+relseg*2);
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sdw = *(unsigned int *)(MEM+staddr+relseg*2);
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TRACE(T_MAP," staddr=%o, sdw=%o\n", staddr, sdw);
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if (sdw & 0x8000)
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fault(SEGFAULT, 2, ea); /* fcode = sdw fault bit set */
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ptaddr = (((sdw & 0x3F)<<10) | (sdw>>22)) << 6;
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if (gvp->pmap32bits) {
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pmaddr = ptaddr + 2*PAGENO(ea);
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pte = mem[pmaddr];
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pte = MEM[pmaddr];
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/* this is probably correct (don't have any references) for
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the 53xx and later machines that support more than 128MB of
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@@ -851,16 +865,16 @@ static pa_t mapva(ea_t ea, ea_t rp, short intacc, unsigned short *access) {
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example). Need to have a mask for each CPU type to make it
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technically correct. */
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ppn = ((mem[pmaddr] & gvp->pmap32mask) << 16) | mem[pmaddr+1];
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ppn = ((MEM[pmaddr] & gvp->pmap32mask) << 16) | MEM[pmaddr+1];
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} else {
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pmaddr = ptaddr + PAGENO(ea);
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pte = mem[pmaddr];
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pte = MEM[pmaddr];
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ppn = pte & 0xFFF;
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}
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TRACE(T_MAP," ptaddr=%o, pmaddr=%o, pte=%o\n", ptaddr, pmaddr, pte);
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if (!(pte & 0x8000))
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fault(PAGEFAULT, 0, ea);
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mem[pmaddr] |= 040000; /* set referenced bit */
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MEM[pmaddr] |= 040000; /* set referenced bit */
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stlbp->access[0] = 7;
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stlbp->access[1] = (sdw >> 12) & 7;
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stlbp->access[STLB_UNMODIFIED_BIT] = 1;
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@@ -868,7 +882,7 @@ static pa_t mapva(ea_t ea, ea_t rp, short intacc, unsigned short *access) {
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stlbp->procid = crs[OWNERL];
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stlbp->seg = seg;
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stlbp->ppn = ppn;
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stlbp->pmep = mem+pmaddr;
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stlbp->pmep = MEM+pmaddr;
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#ifndef NOTRACE
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stlbp->load_ic = gvp->instcount;
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#endif
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@@ -976,9 +990,9 @@ const static unsigned int mapio(ea_t ea) {
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/* these are I/O versions of get/put that use the IOTLB rather than
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the STLB */
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#define get16io(ea) mem[mapio((ea))]
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#define get32io(ea) *(unsigned int *)(mem+mapio((ea)))
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#define put16io(word,ea) mem[mapio((ea))] = word
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#define get16io(ea) MEM[mapio((ea))]
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#define get32io(ea) *(unsigned int *)(MEM+mapio((ea)))
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#define put16io(word,ea) MEM[mapio((ea))] = word
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/* these are shorthand macros for get/put that use the current program
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counter - the typical usage - or Ring 0, the other typical case.
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@@ -1010,6 +1024,12 @@ const static unsigned int mapio(ea_t ea) {
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- in V-mode long instruction address calculation or execution
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get16trap handles 16-bit fetches that are KNOWN to be address traps
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get16r handles 16-bit fetches that used a passed-in virtual address;
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(only the ring part is used from this address).
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VERY IMPORTANT: get16r _cannot_ use the supercache! You don't want to
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cache Ring 0 accesses to data, then let Ring 3 use the cache!
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*/
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@@ -1025,26 +1045,26 @@ static inline unsigned short get16(ea_t ea) {
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/* idle loop runs faster if this is enabled, but executable is 27K
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bigger and programs (ADD) run slower. Maybe inline expansions of
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get16 & fastmap are too big for cache (?) */
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return mem[fastmap(ea, RP, RACC)];
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return MEM[fastmap(ea, RP, RACC)];
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#endif
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#ifdef FAST
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#ifndef NOTRACE
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gvp->supercalls++;
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#endif
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if ((ea & 0x0FFFFC00) == eap->vpn) {
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if ((ea & 0x0FFFFC00) == (eap->vpn & 0x0FFFFFFF)) {
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TRACE(T_MAP, " get16: supercached %o/%o [%s]\n", ea>>16, ea&0xFFFF, brp_name());
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return eap->memp[ea & 0x3FF];
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} else {
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#ifndef NOTRACE
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gvp->supermisses++;
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#endif
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eap->memp = mem + (mapva(ea, RP, RACC, &access) & 0xFFFFFC00);
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eap->vpn = ea & 0x0FFFFC00;
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eap->memp = MEM + (mapva(ea, RP, RACC, &access) & 0xFFFFFC00);
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eap->vpn = (ea & 0x0FFFFC00) | (access << 28);
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return eap->memp[ea & 0x3FF];
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}
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#else
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return mem[mapva(ea, RP, RACC, &access)];
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return MEM[mapva(ea, RP, RACC, &access)];
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#endif
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}
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@@ -1082,14 +1102,37 @@ static unsigned short get16r(ea_t ea, ea_t rpring) {
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warn("address trap in get16r");
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#endif
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return mem[mapva(ea, rpring, RACC, &access)];
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return MEM[mapva(ea, rpring, RACC, &access)];
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}
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static unsigned int get32(ea_t ea) {
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/* get32m always uses the map and isn't inlined */
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static unsigned int get32m(ea_t ea) {
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pa_t pa;
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unsigned short access;
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unsigned short m[2];
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#if DBG
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if (ea & 0x80000000) /* check for live register access */
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warn("address trap in get32m");
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#endif
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#ifndef NOTRACE
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gvp->supermisses++;
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#endif
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if ((ea & 01777) <= 01776) {
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eap->memp = MEM + (mapva(ea, RP, RACC, &access) & 0xFFFFFC00);
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eap->vpn = (ea & 0x0FFFFC00) | (access << 28);
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return *(unsigned int *)&eap->memp[ea & 0x3FF];
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}
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return (get16(ea) << 16) | get16(INCVA(ea,1));
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}
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/* get32 tries to use the supercache and is inlined */
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static inline unsigned int get32(ea_t ea) {
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pa_t pa;
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#if DBG
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if (ea & 0x80000000) /* check for live register access */
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warn("address trap in get32");
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@@ -1100,24 +1143,16 @@ static unsigned int get32(ea_t ea) {
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gvp->supercalls++;
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#endif
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if ((ea & 01777) <= 01776)
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if ((ea & 0x0FFFFC00) == eap->vpn) {
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if ((ea & 0x0FFFFC00) == (eap->vpn & 0x0FFFFFFF)) {
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TRACE(T_MAP, " get32: supercached %o/%o [%s]\n", ea>>16, ea&0xFFFF, brp_name());
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return *(unsigned int *)&eap->memp[ea & 0x3FF];
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} else {
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#ifndef NOTRACE
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gvp->supermisses++;
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#endif
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eap->memp = mem + (mapva(ea, RP, RACC, &access) & 0xFFFFFC00);
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eap->vpn = ea & 0x0FFFFC00;
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return *(unsigned int *)&eap->memp[ea & 0x3FF];
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}
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/* XXX: could see if 1st word is supercached -- painful! */
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return (get16(ea) << 16) | get16(INCVA(ea,1));
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return get32m(ea);
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#else
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pa = mapva(ea, RP, RACC, &access);
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if ((ea & 01777) <= 01776)
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return *(unsigned int *)(mem+pa);
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return (mem[pa] << 16) | get16(INCVA(ea,1));
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return *(unsigned int *)(MEM+pa);
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return (MEM[pa] << 16) | get16(INCVA(ea,1));
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#endif
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}
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@@ -1133,8 +1168,8 @@ static unsigned int get32r(ea_t ea, ea_t rpring) {
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pa = mapva(ea, rpring, RACC, &access);
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if ((pa & 01777) <= 01776)
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return *(unsigned int *)(mem+pa);
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return (mem[pa] << 16) | get16r(INCVA(ea,1), rpring);
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return *(unsigned int *)(MEM+pa);
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return (MEM[pa] << 16) | get16r(INCVA(ea,1), rpring);
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}
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static long long get64r(ea_t ea, ea_t rpring) {
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@@ -1152,36 +1187,36 @@ static long long get64r(ea_t ea, ea_t rpring) {
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pa = mapva(ea, rpring, RACC, &access);
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#if FAST
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if ((ea & 01777) <= 01774) { /* no page wrap */
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*(int *)(m+0) = *(int *)(mem+pa);
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*(int *)(m+2) = *(int *)(mem+pa+2);
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*(int *)(m+0) = *(int *)(MEM+pa);
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*(int *)(m+2) = *(int *)(MEM+pa+2);
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} else /* wraps page (maybe seg too) */
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switch (ea & 3) {
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case 1:
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m[0] = mem[pa];
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*(int *)(m+1) = *(int *)(mem+pa+1);
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m[0] = MEM[pa];
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*(int *)(m+1) = *(int *)(MEM+pa+1);
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pa = mapva(INCVA(ea,3), rpring, RACC, &access);
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m[3] = mem[pa];
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m[3] = MEM[pa];
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break;
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case 2:
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*(int *)(m+0) = *(int *)(mem+pa);
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*(int *)(m+0) = *(int *)(MEM+pa);
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pa = mapva(INCVA(ea,2), rpring, RACC, &access);
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*(int *)(m+2) = *(int *)(mem+pa);
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*(int *)(m+2) = *(int *)(MEM+pa);
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break;
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case 3:
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m[0] = mem[pa];
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m[0] = MEM[pa];
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pa = mapva(INCVA(ea,1), rpring, RACC, &access);
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*(int *)(m+1) = *(int *)(mem+pa);
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m[3] = mem[pa+2];
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*(int *)(m+1) = *(int *)(MEM+pa);
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m[3] = MEM[pa+2];
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break;
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default:
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fatal("Page cross error in get64r");
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}
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#else
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if ((pa & 01777) <= 01774) { /* no page wrap */
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*(int *)(m+0) = *(int *)(mem+pa);
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*(int *)(m+2) = *(int *)(mem+pa+2);
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*(int *)(m+0) = *(int *)(MEM+pa);
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*(int *)(m+2) = *(int *)(MEM+pa+2);
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} else {
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m[0] = mem[pa];
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m[0] = MEM[pa];
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m[1] = get16r(INCVA(ea,1), rpring);
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m[2] = get16r(INCVA(ea,2), rpring);
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m[3] = get16r(INCVA(ea,3), rpring);
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@@ -1216,8 +1251,8 @@ unsigned short iget16t(ea_t ea) {
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unsigned short access;
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if (*(int *)&ea > 0) {
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gvp->brp[RPBR].vpn = ea & 0x0FFFFC00;
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gvp->brp[RPBR].memp = mem + (mapva(ea, RP, RACC, &access) & 0xFFFFFC00);
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gvp->brp[RPBR].memp = MEM + (mapva(ea, RP, RACC, &access) & 0xFFFFFC00);
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gvp->brp[RPBR].vpn = (ea & 0x0FFFFC00) | (access << 28);
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return gvp->brp[RPBR].memp[ea & 0x3FF];
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}
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return get16trap(ea);
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@@ -1226,7 +1261,7 @@ unsigned short iget16t(ea_t ea) {
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static inline unsigned short iget16(ea_t ea) {
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unsigned short access;
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if ((ea & 0x8FFFFC00) == gvp->brp[RPBR].vpn)
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if ((ea & 0x8FFFFC00) == (gvp->brp[RPBR].vpn & 0x0FFFFFFF))
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||||
return gvp->brp[RPBR].memp[ea & 0x3FF];
|
||||
else
|
||||
return iget16t(ea);
|
||||
@@ -1247,15 +1282,26 @@ static inline put16(unsigned short value, ea_t ea) {
|
||||
|
||||
#ifdef FAST
|
||||
|
||||
/* there is no access stored in the supercache, so writes
|
||||
always have to go through mapva, but the cache is updated
|
||||
so that the next read might avoid mapva */
|
||||
#ifndef NOTRACE
|
||||
gvp->supercalls++;
|
||||
#endif
|
||||
|
||||
eap->memp = mem + (mapva(ea, RP, WACC, &access) & 0xFFFFFC00);
|
||||
eap->vpn = ea & 0x0FFFFC00;
|
||||
eap->memp[ea & 0x3FF] = value;
|
||||
/* access bits are stored in bits 2-4 of the supercache vpn.
|
||||
write access is indicated by bit 4 (MSB = bit 1) */
|
||||
|
||||
if ((ea & 0x0FFFFC00) == (eap->vpn & 0x0FFFFFFF) && (eap->vpn & 0x10000000)) {
|
||||
TRACE(T_MAP, " put16: supercached %o/%o [%s]\n", ea>>16, ea&0xFFFF, brp_name());
|
||||
eap->memp[ea & 0x3FF] = value;
|
||||
} else {
|
||||
#ifndef NOTRACE
|
||||
gvp->supermisses++;
|
||||
#endif
|
||||
eap->memp = MEM + (mapva(ea, RP, WACC, &access) & 0xFFFFFC00);
|
||||
eap->vpn = (ea & 0x0FFFFC00) | (access << 28);
|
||||
eap->memp[ea & 0x3FF] = value;
|
||||
}
|
||||
#else
|
||||
mem[mapva(ea, RP, WACC, &access)] = value;
|
||||
MEM[mapva(ea, RP, WACC, &access)] = value;
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -1267,7 +1313,7 @@ static put16r(unsigned short value, ea_t ea, ea_t rpring) {
|
||||
warn("address trap in put16r");
|
||||
#endif
|
||||
|
||||
mem[mapva(ea, rpring, WACC, &access)] = value;
|
||||
MEM[mapva(ea, rpring, WACC, &access)] = value;
|
||||
}
|
||||
|
||||
/* put16t handles stores that ARE address traps */
|
||||
@@ -1318,14 +1364,36 @@ static put32(unsigned int value, ea_t ea) {
|
||||
warn("address trap in put32");
|
||||
#endif
|
||||
|
||||
#ifdef FAST
|
||||
#ifndef NOTRACE
|
||||
gvp->supercalls++;
|
||||
#endif
|
||||
if ((ea & 01777) <= 01776) {
|
||||
if ((ea & 0x0FFFFC00) == (eap->vpn & 0x0FFFFFFF) && (eap->vpn & 0x10000000)) {
|
||||
TRACE(T_MAP, " put32: supercached %o/%o [%s]\n", ea>>16, ea&0xFFFF, brp_name());
|
||||
*(unsigned int *)&eap->memp[ea & 0x3FF] = value;
|
||||
} else {
|
||||
#ifndef NOTRACE
|
||||
gvp->supermisses++;
|
||||
#endif
|
||||
eap->memp = MEM + (mapva(ea, RP, WACC, &access) & 0xFFFFFC00);
|
||||
eap->vpn = (ea & 0x0FFFFC00) | (access << 28);
|
||||
*(unsigned int *)&eap->memp[ea & 0x3FF] = value;
|
||||
}
|
||||
} else {
|
||||
put16(value >> 16, ea);
|
||||
put16(value & 0xFFFF, INCVA(ea,1));
|
||||
}
|
||||
#else
|
||||
pa = mapva(ea, RP, WACC, &access);
|
||||
if ((pa & 01777) <= 01776)
|
||||
*(unsigned int *)(mem+pa) = value;
|
||||
*(unsigned int *)(MEM+pa) = value;
|
||||
else {
|
||||
m = (void *)&value;
|
||||
mem[pa] = m[0];
|
||||
MEM[pa] = m[0];
|
||||
put16(m[1], INCVA(ea,1));
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
static put32r(unsigned int value, ea_t ea, ea_t rpring) {
|
||||
@@ -1340,10 +1408,10 @@ static put32r(unsigned int value, ea_t ea, ea_t rpring) {
|
||||
|
||||
pa = mapva(ea, rpring, WACC, &access);
|
||||
if ((pa & 01777) <= 01776)
|
||||
*(unsigned int *)(mem+pa) = value;
|
||||
*(unsigned int *)(MEM+pa) = value;
|
||||
else {
|
||||
m = (void *)&value;
|
||||
mem[pa] = m[0];
|
||||
MEM[pa] = m[0];
|
||||
put16r(m[1], INCVA(ea,1), rpring);
|
||||
}
|
||||
}
|
||||
@@ -1362,10 +1430,10 @@ static put64r(long long value, ea_t ea, ea_t rpring) {
|
||||
|
||||
pa = mapva(ea, rpring, WACC, &access);
|
||||
if ((pa & 01777) <= 01774)
|
||||
*(long long *)(mem+pa) = value;
|
||||
*(long long *)(MEM+pa) = value;
|
||||
else {
|
||||
m = (void *)&value;
|
||||
mem[pa] = m[0];
|
||||
MEM[pa] = m[0];
|
||||
put16r(m[1], INCVA(ea,1), rpring);
|
||||
put16r(m[2], INCVA(ea,2), rpring);
|
||||
put16r(m[3], INCVA(ea,3), rpring);
|
||||
@@ -1444,7 +1512,7 @@ static int rtq(ea_t qcbea, unsigned short *qent, ea_t rp) {
|
||||
else {
|
||||
RESTRICTR(rp);
|
||||
/* XXX: this should probably go through mapio */
|
||||
*qent = mem[qentea];
|
||||
*qent = MEM[qentea];
|
||||
}
|
||||
qtop = (qtop & ~qmask) | ((qtop+1) & qmask);
|
||||
put16r(qtop & 0xFFFF, qcbea, rp);
|
||||
@@ -1471,7 +1539,7 @@ static int abq(ea_t qcbea, unsigned short qent, ea_t rp) {
|
||||
else {
|
||||
RESTRICTR(rp);
|
||||
/* XXX: this should probably go through mapio */
|
||||
mem[qentea] = qent;
|
||||
MEM[qentea] = qent;
|
||||
}
|
||||
put16r(qtemp, qcbea+1, rp);
|
||||
return 1;
|
||||
@@ -2124,15 +2192,15 @@ static memdump(int start, int end) {
|
||||
|
||||
TRACEA("\nSector 0:\n");
|
||||
for (ea=0; ea<01000; ea=ea+8)
|
||||
if (mem[ea]|mem[ea+1]|mem[ea+2]|mem[ea+3]|mem[ea+4]|mem[ea+5]|mem[ea+6]|mem[ea+7])
|
||||
TRACEA("%3o: %6o %6o %6o %6o %6o %6o %6o %6o\n", ea, mem[ea], mem[ea+1], mem[ea+2], mem[ea+3], mem[ea+4], mem[ea+5], mem[ea+6], mem[ea+7]);
|
||||
if (MEM[ea]|MEM[ea+1]|MEM[ea+2]|MEM[ea+3]|MEM[ea+4]|MEM[ea+5]|MEM[ea+6]|MEM[ea+7])
|
||||
TRACEA("%3o: %6o %6o %6o %6o %6o %6o %6o %6o\n", ea, MEM[ea], MEM[ea+1], MEM[ea+2], MEM[ea+3], MEM[ea+4], MEM[ea+5], MEM[ea+6], MEM[ea+7]);
|
||||
|
||||
/* dump main memory for debugging */
|
||||
|
||||
TRACEA("\nMain memory:\n");
|
||||
for (ea=start; ea<=end; ea=ea+8)
|
||||
if (mem[ea]|mem[ea+1]|mem[ea+2]|mem[ea+3]|mem[ea+4]|mem[ea+5]|mem[ea+6]|mem[ea+7])
|
||||
TRACEA("%o: %6o %6o %6o %6o %6o %6o %6o %6o\n", ea, mem[ea], mem[ea+1], mem[ea+2], mem[ea+3], mem[ea+4], mem[ea+5], mem[ea+6], mem[ea+7]);
|
||||
if (MEM[ea]|MEM[ea+1]|MEM[ea+2]|MEM[ea+3]|MEM[ea+4]|MEM[ea+5]|MEM[ea+6]|MEM[ea+7])
|
||||
TRACEA("%o: %6o %6o %6o %6o %6o %6o %6o %6o\n", ea, MEM[ea], MEM[ea+1], MEM[ea+2], MEM[ea+3], MEM[ea+4], MEM[ea+5], MEM[ea+6], MEM[ea+7]);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -2150,7 +2218,7 @@ static dumpsegs() {
|
||||
TRACEA("DTAR %d: register=%o, size=%d, seg table addr=%o\n", i, dtar, nsegs, staddr);
|
||||
for (seg=0; seg<nsegs; seg++) {
|
||||
segno = (i<<10)+seg;
|
||||
sdw = *(unsigned int *)(mem+staddr);
|
||||
sdw = *(unsigned int *)(MEM+staddr);
|
||||
ptaddr = ((sdw & 0x3F)<<10) | (sdw>>22);
|
||||
TRACEA("Segment '%o: F=%d, R1:%o R3:%o PT = %o\n", segno, (sdw>>15)&1, (sdw>>12)&7, (sdw>>6)&7, ptaddr);
|
||||
xxx = (sdw>>16)&0x3F;
|
||||
@@ -2158,7 +2226,7 @@ static dumpsegs() {
|
||||
if (ptaddr != 0)
|
||||
for (page=0; page<64; page++) {
|
||||
pmaddr = (ptaddr<<6) + page;
|
||||
pte = mem[pmaddr];
|
||||
pte = MEM[pmaddr];
|
||||
TRACEA(" Seg %o page %d: pmaddr=%o, V=%d R=%d U=%d S=%d PPA=%o\n", segno, page, pmaddr, pte>>15, (pte>>14)&1, (pte>>13)&1, (pte>>12)&1, pte&0xFFF);
|
||||
}
|
||||
staddr += 2;
|
||||
@@ -2493,9 +2561,9 @@ static pcl (ea_t ecbea) {
|
||||
invalidate_brp();
|
||||
if ((ecbea & 0xF) != 0)
|
||||
fault(ACCESSFAULT, 0, ecbea);
|
||||
memcpy(ecb,mem+pa,sizeof(ecb));
|
||||
memcpy(ecb,MEM+pa,sizeof(ecb));
|
||||
} else if ((pa & 01777) <= 01750) {
|
||||
memcpy(ecb,mem+pa,sizeof(ecb));
|
||||
memcpy(ecb,MEM+pa,sizeof(ecb));
|
||||
} else {
|
||||
*(long long *)(ecb+0) = get64(ecbea+0);
|
||||
*(long long *)(ecb+4) = get64(ecbea+4);
|
||||
@@ -3880,12 +3948,11 @@ main (int argc, char **argv) {
|
||||
|
||||
/* initialize global variables */
|
||||
|
||||
if (sizeof(gv) > 16*1024)
|
||||
printf("em: size of global vars = %d\n", sizeof(gv));
|
||||
|
||||
gvp = &gv;
|
||||
gvp->traceflags = 0;
|
||||
gvp->savetraceflags = 0;
|
||||
gvp->traceuser = 0;
|
||||
gvp->traceseg = 0;
|
||||
gvp->numtraceprocs = 0;
|
||||
gvp->physmem = physmem;
|
||||
gvp->intvec = -1;
|
||||
gvp->instcount = 0;
|
||||
gvp->inhcount = 0;
|
||||
@@ -3895,6 +3962,11 @@ main (int argc, char **argv) {
|
||||
gvp->mapvamisses = 0;
|
||||
gvp->supercalls = 0;
|
||||
gvp->supermisses = 0;
|
||||
gvp->traceflags = 0;
|
||||
gvp->savetraceflags = 0;
|
||||
gvp->traceuser = 0;
|
||||
gvp->traceseg = 0;
|
||||
gvp->numtraceprocs = 0;
|
||||
invalidate_brp();
|
||||
eap = &gvp->brp[0];
|
||||
|
||||
@@ -3952,7 +4024,7 @@ main (int argc, char **argv) {
|
||||
gvp->stlb[i].seg = 0xFFFF; /* marker for invalid STLB entry */
|
||||
for (i=0; i < IOTLBENTS; i++)
|
||||
gvp->iotlb[i].valid = 0;
|
||||
bzero(mem, 64*1024*2); /* zero first 64K words */
|
||||
bzero(MEM, 64*1024*2); /* zero first 64K words */
|
||||
|
||||
verbose = 0;
|
||||
domemdump = 0;
|
||||
@@ -4230,7 +4302,7 @@ For disk boots, the last 3 digits can be:\n\
|
||||
/* read memory image from SA to EA inclusive */
|
||||
|
||||
nw = rvec[1]-rvec[0]+1;
|
||||
if ((nw2=read(bootfd, mem+rvec[0], nw*2)) == -1) {
|
||||
if ((nw2=read(bootfd, MEM+rvec[0], nw*2)) == -1) {
|
||||
perror("Error reading memory image");
|
||||
fatal(NULL);
|
||||
}
|
||||
@@ -4513,7 +4585,7 @@ xec:
|
||||
|
||||
if ((inst & 036000) == 0) {
|
||||
TRACE(T_INST, " generic class %d\n", inst>>14);
|
||||
goto *gvp->disp_gen[GENIX(inst)];
|
||||
goto *disp_gen[GENIX(inst)];
|
||||
}
|
||||
|
||||
/* get x bit and adjust opcode so that PMA manual opcode
|
||||
@@ -4887,7 +4959,7 @@ d_calf: /* 000705 */
|
||||
*/
|
||||
|
||||
#define ZSTEP(zea, zlen, zcp, zclen, zacc) \
|
||||
zcp = (unsigned char *) (mem+mapva(zea, RP, zacc, &zaccess)); \
|
||||
zcp = (unsigned char *) (MEM+mapva(zea, RP, zacc, &zaccess)); \
|
||||
zclen = 2048 - (zea & 01777)*2; \
|
||||
if (zea & EXTMASK32) { \
|
||||
zcp++; \
|
||||
@@ -8897,7 +8969,7 @@ d_irs: /* 01200 */
|
||||
stopwatch_push(&sw_irs);
|
||||
TRACE(T_FLOW, " IRS\n");
|
||||
if (*(int *)&ea >= 0)
|
||||
utempa = ++mem[mapva(ea, RP, WACC, &access)];
|
||||
utempa = ++MEM[mapva(ea, RP, WACC, &access)];
|
||||
else {
|
||||
utempa = get16t(ea) + 1;
|
||||
put16t(utempa, ea);
|
||||
@@ -8911,8 +8983,8 @@ d_ima: /* 01300 */
|
||||
TRACE(T_FLOW, " IMA\n");
|
||||
if (*(int *)&ea >= 0) {
|
||||
pa = mapva(ea, RP, WACC, &access);
|
||||
utempa = mem[pa];
|
||||
mem[pa] = crs[A];
|
||||
utempa = MEM[pa];
|
||||
MEM[pa] = crs[A];
|
||||
} else {
|
||||
utempa = get16t(ea);
|
||||
put16t(crs[A],ea);
|
||||
|
||||
8
emdev.h
8
emdev.h
@@ -1513,7 +1513,7 @@ int devcp (int class, int func, int device) {
|
||||
if (gvp->instcount-previnstcount > gvp->instpermsec*1000*5) {
|
||||
gvp->instpermsec = (gvp->instcount-previnstcount) /
|
||||
((tv.tv_sec-prev_tv.tv_sec-1)*1000 + (tv.tv_usec+1000000-prev_tv.tv_usec)/1000);
|
||||
//printf("instcount = %d, previnstcount = %d, diff=%d, instpermsec=%d\n", gvp->instcount, previnstcount, gvp->instcount-previnstcount, gvp->instpermsec);
|
||||
//printf("gvp->instcount = %d, previnstcount = %d, diff=%d, instpermsec=%d\n", gvp->instcount, previnstcount, gvp->instcount-previnstcount, gvp->instpermsec);
|
||||
#ifdef NOIDLE
|
||||
printf("\ninstpermsec=%d\n", gvp->instpermsec);
|
||||
#endif
|
||||
@@ -1909,9 +1909,9 @@ int devdisk (int class, int func, int device) {
|
||||
if ((dmaaddr & 01777) || dmanw > 1024)
|
||||
iobufp = iobuf;
|
||||
else
|
||||
iobufp = mem+mapio(dmaaddr);
|
||||
iobufp = MEM+mapio(dmaaddr);
|
||||
else
|
||||
iobufp = mem+dmaaddr;
|
||||
iobufp = MEM+dmaaddr;
|
||||
if (hashp != NULL) {
|
||||
memcpy((char *)iobufp, hashp, dmanw*2);
|
||||
hashp += dmanw*2;
|
||||
@@ -1929,7 +1929,7 @@ int devdisk (int class, int func, int device) {
|
||||
for (i=0; i<dmanw; i++)
|
||||
iobuf[i] = get16io(dmaaddr+i);
|
||||
} else
|
||||
iobufp = mem+dmaaddr;
|
||||
iobufp = MEM+dmaaddr;
|
||||
if (hashp != NULL) {
|
||||
memcpy(hashp, (char *)iobufp, dmanw*2);
|
||||
hashp += dmanw*2;
|
||||
|
||||
Reference in New Issue
Block a user