8 Commits

Author	SHA1	Message	Date
Jim	f9d4f6f3bb	trace improvements, PCL indirect bit offset bug (SAC odd char bug) + ... added T_TERM for system terminal output tracing added specific user tracing: - 2-digit number after trace (user number) - 6-digit octal number = OWNERL (for devices) added specific procedure tracing major bug in PCL: indirect bit offsets not working, causing SAC JIM:PDALURW to be SAC JIM:PAUW	2007-03-01 00:00:00 -05:00
Jim	09b9592915	WAIT register save shouldn't save all registers like PX does + ... need to restore interval timer when new process dispatched process level was incorrect when new process dispatched changes setting process abort flag in PCB when timer overflows	2005-09-19 00:00:00 -04:00
Jim	5ab1209f0a	INCVA macro for segment wraparound, PX work, added --cpuid option	2005-06-16 00:00:00 -04:00
Jim	997332c487	first implementation of process exchange, WAIT, NFY + ... added restricted instruction checking added CALF more PCL work	2005-06-13 00:00:00 -04:00
Jim	7f433b9b27	implemented ARGT for interruptable PCL, more work on PCL	2005-06-11 00:00:00 -04:00
Jim	22f4c22f8f	virtual address translation, fault handling code + ... tracing for address translation, disk I/O, and PCL field address, field length, and load/store character instructions queue instructions more work on setting C & L bits correctly	2005-06-07 00:00:00 -04:00
Jim	3763da4cbe	added live register access to memory get/put functions ... added live register access flag to effective address calculations first attempt at complete 64V address calculation first RSAV/RRST, STAC/STLC, LPSW, LDLR/STLR, EIO more shift instruction work	2005-05-24 00:00:00 -04:00
Jim	efc25712b5	defined register file with regs.h ... began using (get,put)16/32/64 functions to access memory instead of mem[] began using crs[] to access current registers instead of mem[]	2005-05-23 00:00:00 -04:00