mirror of
https://github.com/prirun/p50em.git
synced 2026-04-28 21:17:32 +00:00
55ea18c85e
added "smart" LRU code to handle multiple register sets expanded registers to handle 8 user, 2 system (10 total) turned off various process-exchange changes that were causing failures only zero first 64K of memory added emulation of ZTRN, ZED, and RTS started I-mode floating point make sure R-mode MPL faults to appease DIAG tests
167 lines
3.2 KiB
C
167 lines
3.2 KiB
C
#define REGSETS 10
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/* these are 16-bit offsets into crs (current register set) */
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#define A 4
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#define B 5
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#define L 4
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#define E 6
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#define S 10
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#define Y 10
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#define YH 10
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#define YL 11
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#define X 14
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#define XH 14
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#define XL 15
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#define FLTH 20
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#define FLTL 21
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#define FLTD 22
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#define FEXP 23
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#define VSC 23
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#define PB 24
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#define PBH 24
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#define PBL 25
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#define SB 26
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#define SBH 26
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#define SBL 27
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#define LB 28
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#define LBH 28
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#define LBL 29
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#define XB 30
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#define XBH 30
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#define XBL 31
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#define DTAR3 32
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#define DTAR2 34
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#define DTAR1 36
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#define DTAR0 38
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#define KEYS 40
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#define MODALS 41
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#define OWNER 42
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#define OWNERH 42
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#define OWNERL 43
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#define FCODE 44
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#define FADDR 46
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#define TIMER 48
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#define TIMERH 48
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#define TIMERL 49
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/* I-mode offsets for 16-bit access to registers, eg, crs[GR0H] */
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#define GR0H 0
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#define GR1H 2
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#define GR2H 4
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#define GR3H 6
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#define GR4H 8
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#define GR5H 10
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#define GR6H 12
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#define GR7H 14
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/* these are 32-bit offsets into crsl (current register set long) */
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#define GR0 0
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#define GR1 1
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#define GR2 2
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#define GR3 3
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#define GR4 4
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#define GR5 5
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#define GR6 6
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#define GR7 7
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#define FAR0 8
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#define FLR0 9
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#define FAR1 10
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#define FLR1 11
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#define FAC0 8
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#define FAC1 10
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#define BR 12
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union {
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int rs[REGSETS][32];
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unsigned short rs16[REGSETS][64];
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/* locs '0-'177 as signed 32-bit integers */
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int s32[32*REGSETS];
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/* locs '0-'177 as unsigned 32-bit integers */
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unsigned int u32[32*REGSETS];
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/* locs '0-'377 as signed 16-bit integers */
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short s16[64*REGSETS];
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/* locs '0-'377 as signed 16-bit integers */
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unsigned short u16[64*REGSETS];
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/* symbolic register file locations */
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struct {
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unsigned int tr0,tr1,tr2,tr3,tr4,tr5,tr6,tr7;
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unsigned int rdmx1,rdmx2;
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unsigned short rdum1[1],ratmpl;
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unsigned int rsgt1,rsgt2,recc1,recc2;
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unsigned short rdum2[1],reoiv,zero,one;
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unsigned int pbsave,rdmx3,rdmx4,c377,rdum3[3];
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unsigned int pswpb;
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unsigned short pswkeys,rdum4[1];
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unsigned short pla,pcba,plb,pcbb;
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unsigned int dswrma;
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unsigned int dswstat;
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unsigned int dswpb,rsavptr;
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unsigned short regdmx[64];
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unsigned int userregs[REGSETS-2][32];
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} sym;
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} regs;
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unsigned short *crs;
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unsigned int *crsl;
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/* define mapping between memory addresses and the current register set */
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unsigned short memtocrs[] = {
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X, /* 0 = X */
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A, /* 1 = A */
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B, /* 2 = B */
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Y, /* 3 = Y */
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FLTH, /* 4 = FAC1/FLTH */
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FLTL, /* 5 = FAC1/FLTL */
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FEXP, /* 6 = FAC1/FEXP */
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-1, /* 7 = PC (this is in the microcode scratch register set - TR7) */
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32, /* 10 = unnamed */
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FCODE, /* 11 = FCODE */
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FADDR+1,/* 12 = FADDR (word) */
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16, /* 13 = unnamed */
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SBH, /* 14 = unnamed (SB seg) */
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SBL, /* 15 = unnamed (SB word) */
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LBH, /* 16 = unnamed (LB seg) */
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LBL}; /* 17 = unnamed (LB word) */
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#define PCBLEV 0
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#define PCBLINK 1
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#define PCBWAIT 2
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#define PCBABT 4
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#define PCBCPU 5
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#define PCBPET 8
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#define PCBDTAR2 10
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#define PCBDTAR3 12
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#define PCBIT 14
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#define PCBMASK 16
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#define PCBKEYS 17
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#define PCBREGS 18
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#define PCBFVEC 50
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#define PCBFVR0 50
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#define PCBFVR1 52
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#define PCBFVR2 54
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#define PCBFVR3 56
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#define PCBFVPF 58
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#define PCBCSFIRST 60
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#define PCBCSNEXT 61
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#define PCBCSLAST 62
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