Jim f0983d6ccb Preserve fault and E bits in EAFA instructions to pass CPUT4 T&M halt ...

at 7753 and 10061.  At 7753, CPUT4 loads -1L into the SB register,
EAFA 1,SB%, then LDLR '12 to get the FAR1 register value.  It expects
it to be -1.  For the test at 10061, EAFA was clearing the E-bit in
FAR1, but the test expected it to be set.  The emulator never uses the
E-bit in the FAR (it only looks at bitno), so it doesn't matter how the
E-bit is set in the register.

2011-08-09 09:04:15 -04:00

devpnc.h

Initial PNC driver (no receive yet), added #ifdefs for trace, allow

2011-07-30 17:06:19 -04:00

dispatch.h

For CPUT4, add LPID (only checks restricted) and mark some other

2011-08-06 09:30:27 -04:00

ea32i.h

More performance tweeaks: get/put(16/32)r, eaxxx()

2007-09-15 00:00:00 -04:00

ea64v.h

Changes for gcc on OSX 10.6, cross compile on Intel

2011-07-18 09:31:14 -04:00

em.c

Preserve fault and E bits in EAFA instructions to pass CPUT4 T&M halt

2011-08-09 09:04:15 -04:00

emdev.h

Initial PNC driver (no receive yet), added #ifdefs for trace, allow

2011-07-30 17:06:19 -04:00

fp.h

FP exceptions, -DNOREG for -O0 and -DBG compiles, perf tweaks, gcov

2007-10-12 00:00:00 -04:00

geom.h

licensing, sys console, fixed rare hang in sleep if IMPS goes to zero

2008-04-25 00:00:00 -04:00

makefile

Initial PNC driver (no receive yet), added #ifdefs for trace, allow

2011-07-30 17:06:19 -04:00

regs.h

FP exceptions, -DNOREG for -O0 and -DBG compiles, perf tweaks, gcov

2007-10-12 00:00:00 -04:00

swap.h

Add an inline swab option to swap.h

2011-06-19 08:56:11 -04:00

Description

Prime 50-Series Emulator

14 MiB

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