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mirror of https://github.com/rcornwell/sims.git synced 2026-01-29 13:11:00 +00:00

IBM360: Added Decimal and Floating point, start of /67 support.

This commit is contained in:
Richard Cornwell
2019-01-12 16:56:24 -05:00
parent aa6e402998
commit 00f4554c8b
4 changed files with 908 additions and 142 deletions

File diff suppressed because it is too large Load Diff

View File

@@ -103,14 +103,15 @@
#define DK_SETSECT 0x23 /* Set sector */
#define DK_MT 0x80 /* Multi track flag */
#define DK_INDEX 0x0100 /* Index seen in command */
#define DK_NOEQ 0x0200 /* Not equal compare */
#define DK_HIGH 0x0400 /* High compare */
#define DK_PARAM 0x0800 /* Parameter in u4 */
#define DK_MSET 0x1000 /* Mode set command already */
#define DK_SHORTSRC 0x2000 /* Last search was short */
#define DK_SRCOK 0x4000 /* Last search good */
#define DK_CYL_DIRTY 0x8000 /* Current cylinder dirty */
#define DK_INDEX 0x00100 /* Index seen in command */
#define DK_NOEQ 0x00200 /* Not equal compare */
#define DK_HIGH 0x00400 /* High compare */
#define DK_PARAM 0x00800 /* Parameter in u4 */
#define DK_MSET 0x01000 /* Mode set command already */
#define DK_SHORTSRC 0x02000 /* Last search was short */
#define DK_SRCOK 0x04000 /* Last search good */
#define DK_CYL_DIRTY 0x08000 /* Current cylinder dirty */
#define DK_DONE 0x10000 /* Write command done, zero fill */
#define DK_MSK_INHWR0 0x00 /* Inhbit writing of HA/R0 */
#define DK_MSK_INHWRT 0x40 /* Inhbit all writes */
@@ -1025,6 +1026,8 @@ sense_end:
if (state == DK_POS_CNT && count == 0) {
sim_debug(DEBUG_DETAIL, dptr, "search ID unit=%d %x %d %x %d\n",
unit, state, count, uptr->u4, data->rec);
sim_debug(DEBUG_DETAIL, dptr, "ID unit=%d %02x %02x %02x %02x %02x %02x %02x %02x\n",
unit, da[0], da[1], da[2], da[3], da[4], da[5], da[6], da[7]);
uptr->u3 &= ~(DK_SRCOK|DK_SHORTSRC|DK_NOEQ|DK_HIGH);
uptr->u3 |= DK_PARAM;
}
@@ -1378,6 +1381,7 @@ rd:
data->tpos++;
state = data->state = DK_POS_CNT;
uptr->u3 |= DK_PARAM;
uptr->u3 &= ~DK_DONE;
} else {
sim_debug(DEBUG_DETAIL, dptr, "Wr CKD unit=%d seq\n", unit);
uptr->u5 |= SNS_CMDREJ | (SNS_INVSEQ << 8);
@@ -1403,6 +1407,7 @@ rd:
if (((uptr->u6 & 0x13) == 0x11 &&
(uptr->u3 & (DK_SHORTSRC|DK_SRCOK)) == DK_SRCOK)) {
uptr->u3 |= DK_PARAM;
uptr->u3 &= ~DK_DONE;
sim_debug(DEBUG_DETAIL, dptr, "WR KD unit=%d %d k=%d d=%d %02x %04x %d\n",
unit, data->rec, data->klen, data->dlen, data->state,
8 + data->klen + data->dlen, count);
@@ -1429,6 +1434,7 @@ rd:
if (((uptr->u6 & 0x3) == 1 && (uptr->u6 & 0xE0) != 0 &&
(uptr->u3 & (DK_SHORTSRC|DK_SRCOK)) == DK_SRCOK)) {
uptr->u3 |= DK_PARAM;
uptr->u3 &= ~DK_DONE;
sim_debug(DEBUG_DETAIL, dptr, "WR D unit=%d %d k=%d d=%d %02x %04x %d\n",
unit, data->rec, data->klen, data->dlen, data->state,
8 + data->klen + data->dlen, count);
@@ -1444,32 +1450,33 @@ wrckd:
if (uptr->u3 & DK_PARAM) {
uptr->u3 &= ~DK_INDEX;
if (state == DK_INDEX) {
uptr->u5 = SNS_TRKOVR << 8;
uptr->u3 &= ~(0xff|DK_PARAM);
chan_end(addr, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
break;
uptr->u5 = SNS_TRKOVR << 8;
uptr->u3 &= ~(0xff|DK_PARAM|DK_DONE);
chan_end(addr, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
break;
} else if ((cmd == DK_WR_KD || cmd == DK_WR_D) && state == DK_POS_DATA
&& data->dlen == 0) {
sim_debug(DEBUG_DETAIL, dptr, "WR EOF unit=%d %x %d %d d=%d\n",
sim_debug(DEBUG_DETAIL, dptr, "WR EOF unit=%d %x %d %d d=%d\n",
unit, state, count, data->rec, data->dlen);
uptr->u3 &= ~(0xff|DK_PARAM);
uptr->u6 = cmd;
chan_end(addr, SNS_CHNEND|SNS_DEVEND|SNS_UNITEXP);
break;
uptr->u3 &= ~(0xff|DK_PARAM|DK_DONE);
uptr->u6 = cmd;
chan_end(addr, SNS_CHNEND|SNS_DEVEND|SNS_UNITEXP);
break;
} else if (state == DK_POS_DATA && data->count == data->dlen) {
uptr->u6 = cmd;
uptr->u3 &= ~(0xff|DK_PARAM);
chan_end(addr, SNS_CHNEND|SNS_DEVEND);
if ((cmd & 0x10) != 0) {
uptr->u6 = cmd;
uptr->u3 &= ~(0xff|DK_PARAM|DK_DONE);
chan_end(addr, SNS_CHNEND|SNS_DEVEND);
if ((cmd & 0x10) != 0) {
for(i = 0; i < 8; i++)
da[i] = 0xff;
}
sim_debug(DEBUG_DETAIL, dptr, "WCKD end unit=%d %d %d %04x\n",
}
sim_debug(DEBUG_DETAIL, dptr, "WCKD end unit=%d %d %d %04x\n",
unit, data->tpos+8, count, data->tpos - data->rpos);
break;
break;
}
if (chan_read_byte(addr, &ch)) {
if (uptr->u3 & DK_DONE || chan_read_byte(addr, &ch)) {
ch = 0;
uptr->u3 |= DK_DONE;
}
sim_debug(DEBUG_DATA, dptr, "Char %02x, %02x %d %d\n", ch, state,
count, data->tpos);
@@ -1482,16 +1489,17 @@ wrckd:
"WCKD count unit=%d %d k=%d d=%d %02x %04x\n",
unit, data->rec, data->klen, data->dlen, data->state,
8 + data->klen + data->dlen);
data->state = DK_POS_KEY;
if (data->klen == 0)
data->state = DK_POS_DATA;
else
data->state = DK_POS_KEY;
data->count = 0;
}
}
break;
case DK_ERASE: /* Erase to end of track */
if (state == DK_POS_AM || state == DK_POS_END) {
if ((state == DK_POS_AM || state == DK_POS_END) && data->count == 0) {
/* Check if command ok based on mask */
i = data->filemsk & DK_MSK_WRT;
if (i == DK_MSK_INHWRT || i == DK_MSK_ALLWRU) {

View File

@@ -115,6 +115,7 @@ typedef struct dib {
#define OP_SSK 0x08
#define OP_ISK 0x09
#define OP_SVC 0x0A
#define OP_BASR 0x0D
#define OP_LPR 0x10
#define OP_LNR 0x11
#define OP_LTR 0x12
@@ -176,6 +177,7 @@ typedef struct dib {
#define OP_AH 0x4A
#define OP_SH 0x4B
#define OP_MH 0x4C
#define OP_BAS 0x4D
#define OP_CVD 0x4E
#define OP_CVB 0x4F
#define OP_ST 0x50
@@ -236,6 +238,9 @@ typedef struct dib {
#define OP_TIO 0x9D
#define OP_HIO 0x9E
#define OP_TCH 0x9F
#define OP_STMC 0xB0
#define OP_LRA 0xB1
#define OP_LMC 0xB8
#define OP_MVN 0xD1
#define OP_MVC 0xD2
#define OP_MVZ 0xD3

View File

@@ -230,6 +230,7 @@ t_opcode optab[] = {
{ OP_SSK, "SSK", RR },
{ OP_ISK, "ISK", RR },
{ OP_SVC, "SVC", RR|IMDOP },
{ OP_BASR, "BASR", RR },
{ OP_LPR, "LPR", RR },
{ OP_LNR, "LNR", RR },
{ OP_LTR, "LTR", RR },
@@ -291,6 +292,7 @@ t_opcode optab[] = {
{ OP_AH, "AH", RX },
{ OP_SH, "SH", RX },
{ OP_MH, "MH", RX },
{ OP_BAS, "BAS", RX },
{ OP_CVD, "CVD", RX },
{ OP_CVB, "CVB", RX },
{ OP_ST, "ST", RX },
@@ -351,6 +353,9 @@ t_opcode optab[] = {
{ OP_TIO, "TIO", SI|ZEROOP },
{ OP_HIO, "HIO", SI|ZEROOP },
{ OP_TCH, "TCH", SI|ZEROOP },
{ OP_STMC, "STMC", RS|TWOOP },
{ OP_LRA, "LRA", RX },
{ OP_LMC, "LMC", RS|TWOOP },
{ OP_MVN, "MVN", SS },
{ OP_MVC, "MVC", SS },
{ OP_MVZ, "MVZ", SS },