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https://github.com/rcornwell/sims.git
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KA10: Fixed KS10 LP20 to work under Tops 20 and Tops 10
This commit is contained in:
Richard Cornwell
@@ -62,7 +62,7 @@
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#define CS1_ONL 0004000 /* Online */
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#define CS1_DVON 0010000 /* DAVFU online */
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#define CS1_UND 0020000 /* Undefined Character */
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#define CS1_PZERO 0030000 /* Page counter zero */
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#define CS1_PZERO 0040000 /* Page counter zero */
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#define CS1_ERR 0100000 /* Errors */
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#define CS1_MOD (CS1_DHOLD|CS1_IE|(CS1_M_FNC << CS1_V_FNC)|CS1_PAR|CS1_GO)
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@@ -287,9 +287,6 @@ lp20_write(DEVICE *dptr, t_addr addr, uint16 data, int32 access)
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struct pdp_dib *dibp = (DIB *)dptr->ctxt;
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int base;
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uint16 temp;
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int ln;
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TMLN *lp;
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int i;
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addr &= dibp->uba_mask;
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sim_debug(DEBUG_DETAIL, dptr, "LP20 write %06o %06o %o\n",
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@@ -338,11 +335,11 @@ lp20_write(DEVICE *dptr, t_addr addr, uint16 data, int32 access)
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case 002: /* LPCSB */
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if (access == BYTE) {
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if (addr & 1) {
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lp20_cs2 &= ~(CS2_GOE);
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lp20_cs2 |= data & CS2_GOE;
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} else {
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lp20_cs2 &= ~(CS2_TEST);
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lp20_cs2 |= data & CS2_TEST;
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} else {
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lp20_cs2 &= ~(CS2_GOE);
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lp20_cs2 |= data & CS2_GOE;
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}
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} else {
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lp20_cs2 &= ~(CS2_TEST|CS2_GOE);
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@@ -376,9 +373,9 @@ lp20_write(DEVICE *dptr, t_addr addr, uint16 data, int32 access)
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case 014: /* LPCOL/LPCBUF */
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if (access == BYTE) {
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if (addr & 1)
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lp20_buf = data & 0377;
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else
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lp20_col = (data >> 8) & 0377;
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else
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lp20_buf = data & 0377;
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} else {
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lp20_buf = data & 0377;
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lp20_col = (data >> 8) & 0377;
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@@ -386,14 +383,14 @@ lp20_write(DEVICE *dptr, t_addr addr, uint16 data, int32 access)
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break;
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case 016: /* LPCSUM/LPPDAT */
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temp = lp20_ram[(int)lp20_buf];
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if (access == BYTE) {
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temp = lp20_ram[(int)lp20_buf];
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if (addr & 1)
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data = data | (temp & 0377);
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else
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data = (temp & 0177400) | data;
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}
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lp20_ram[(int)lp20_buf] = data;
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lp20_ram[(int)lp20_buf] = data & 07777;
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break;
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}
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lp20_update_chkirq(&lp20_unit, 0, 0);
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@@ -406,9 +403,7 @@ lp20_read(DEVICE *dptr, t_addr addr, uint16 *data, int32 access)
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struct pdp_dib *dibp = (DIB *)dptr->ctxt;
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int base;
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uint16 temp;
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int ln;
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TMLN *lp;
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int i;
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int par;
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addr &= dibp->uba_mask;
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switch (addr & 016) {
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@@ -437,7 +432,12 @@ lp20_read(DEVICE *dptr, t_addr addr, uint16 *data, int32 access)
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break;
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case 012: /* LPRDAT */
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*data = lp20_ram[lp20_buf];
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temp = lp20_ram[lp20_buf] & 07777;
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par = (temp >> 8) ^ (temp >> 4) ^ temp;
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par = (par >> 2) ^ par;
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par ^= par >> 1;
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if ((par & 1) != 0)
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temp |= LP20_RAM_RAP;
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break;
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case 014: /* LPCOL/LPCBUF */
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@@ -500,6 +500,7 @@ lp20_output(UNIT *uptr, char c) {
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if (c == 0)
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return;
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lp20_data = c & 0377;
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if (lp20_col == 132)
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lp20_printline(uptr, 1);
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/* Map lower to upper case if uppercase only */
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@@ -544,13 +545,11 @@ lp20_update_chkirq (UNIT *uptr, int done, int irq)
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if (uptr->flags & UNIT_ATT) {
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lp20_cs1 |= CS1_ONL;
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lp20_cs2 &= ~CS2_OFFL;
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lp20_cs2 &= ~(CS2_OFFL|CS2_NRDY);
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} else {
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lp20_cs1 &= ~(CS1_DONE|CS1_ONL);
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lp20_cs2 |= CS2_OFFL;
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lp20_cs1 &= ~(CS1_ONL|CS1_DONE);
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lp20_cs2 |= CS2_NRDY|CS2_OFFL;
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}
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if (lp20_cs2 & CS2_ERR)
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lp20_cs1 |= CS1_ERR;
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if ((lp20_cs1 & CS1_IE) && (irq || (lp20_cs1 & CS1_DONE)))
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uba_set_irq(dibp);
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else
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@@ -569,8 +568,8 @@ lp20_update_ready(UNIT *uptr, uint16 setrdy, uint16 clrrdy)
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uint16 new_cs1 = (lp20_cs1 | setrdy) & ~clrrdy;
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if ((new_cs1 ^ lp20_cs1) & (CS1_ONL|CS1_DVON) && !sim_is_active(uptr)) {
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if (new_cs1 & CS1_IE)
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uba_set_irq(dibp);
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if (new_cs1 & CS1_IE)
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uba_set_irq(dibp);
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}
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if (new_cs1 & CS1_DVON)
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lp20_cs2 &= ~CS2_DVOF;
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@@ -591,7 +590,7 @@ lp20_svc (UNIT *uptr)
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uint16 ram_ch;
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uint16 par;
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if (fnc != FNC_TEST && (uptr->flags & UNIT_ATT) == 0) {
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if (fnc == FNC_PRINT && (uptr->flags & UNIT_ATT) == 0) {
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lp20_cs1 |= CS1_ERR;
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/* Set error */
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lp20_cs1 &= ~CS1_GO;
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@@ -619,15 +618,6 @@ lp20_svc (UNIT *uptr)
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switch(fnc) {
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case FNC_PRINT:
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ram_ch = lp20_ram[(int)lp20_buf];
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/* Check parity on RAM */
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ram_ch &= ~(LP20_RAM_RAP);
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par = (ram_ch >> 8) ^ (ram_ch >> 4) ^ ram_ch;
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par = (par >> 2) ^ par;
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par ^= par >> 1;
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if ((par & 1) == 0)
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ram_ch |= LP20_RAM_RAP;
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if (ram_ch != lp20_ram[(int)lp20_buf])
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lp20_cs2 |= CS2_RPE;
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/* If previous was delimiter or translation do it */
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if (lp20_cs1 & CS1_DHOLD || (ram_ch &(LP20_RAM_DEL|LP20_RAM_TRN)) != 0) {
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ch = ram_ch & LP20_RAM_CHR;
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@@ -701,7 +691,7 @@ lp20_svc (UNIT *uptr)
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if (lp20_cs1 & CS1_GO)
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sim_activate(uptr, 600);
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else
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lp20_update_chkirq (uptr, 1, 1);
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lp20_update_chkirq (uptr, lp20_wcnt == 0, 1);
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return SCPE_OK;
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case FNC_TEST:
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@@ -716,6 +706,7 @@ lp20_svc (UNIT *uptr)
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lp20_duvfa_state = 1;
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lp20_index = 0;
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lp20_odd = 0;
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lp20_cs2 &= ~CS2_DVOF;
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} else if (lp20_buf == 0357) { /* Stop DVU load */
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lp20_duvfa_state = 0;
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lp20_vfu[lp20_index] = 010000;
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@@ -739,10 +730,10 @@ lp20_svc (UNIT *uptr)
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case FNC_RAM:
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if (lp20_odd) {
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lp20_ram[lp20_index] = (lp20_ram[lp20_index] & 0377) | ((lp20_buf & 0377) << 8);
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lp20_ram[lp20_index] = (lp20_ram[lp20_index] & 0377) | ((lp20_buf & 017) << 8);
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lp20_index++;
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} else {
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lp20_ram[lp20_index] = (lp20_ram[lp20_index] & 0177400) | (lp20_buf & 0377);
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lp20_ram[lp20_index] = (lp20_ram[lp20_index] & 07400) | (lp20_buf & 0377);
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}
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lp20_odd = !lp20_odd;
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break;
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@@ -759,7 +750,7 @@ lp20_svc (UNIT *uptr)
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t_stat lp20_init (UNIT *uptr)
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{
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lp20_cs1 = (lp20_cs1 & CS1_DVON) | CS1_DONE;
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lp20_cs2 = lp20_cs2 & (CS2_OVFU |CS2_DVOF);
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lp20_cs2 = lp20_cs2 & (CS2_OFFL|CS2_DVOF);
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lp20_col = 0;
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lp20_ba = 0;
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lp20_wcnt = 0;
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@@ -814,8 +805,10 @@ t_stat lp20_reset (DEVICE *dptr)
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lp20_ram[i] |= LP20_RAM_RAP;
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}
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sim_cancel (uptr); /* deactivate unit */
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if (uptr->flags & UNIT_ATT)
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if (uptr->flags & UNIT_ATT) {
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lp20_update_ready(uptr, CS1_ONL, 0);
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lp20_update_chkirq (uptr, 1, 0);
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}
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return SCPE_OK;
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}
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@@ -827,8 +820,8 @@ t_stat lp20_attach (UNIT *uptr, CONST char *cptr)
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sim_switches |= SWMASK ('A'); /* Position to EOF */
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r = attach_unit (uptr, cptr);
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if (r == SCPE_OK) {
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lp20_cs1 |= CS1_ONL;
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lp20_cs2 &= ~CS2_OFFL;
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lp20_update_ready(uptr, CS1_ONL, 0);
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lp20_update_chkirq (uptr, 1, 1);
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}
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return r;
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}
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@@ -838,9 +831,8 @@ t_stat lp20_attach (UNIT *uptr, CONST char *cptr)
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t_stat lp20_detach (UNIT *uptr)
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{
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sim_cancel (uptr); /* deactivate unit */
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lp20_cs1 &= ~(CS1_DONE|CS1_ONL|CS1_GO);
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lp20_cs2 |= CS2_OFFL;
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lp20_update_chkirq (uptr, 1, 0);
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lp20_update_ready(uptr, 0, CS1_ONL);
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lp20_update_chkirq (uptr, 1, 1);
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return detach_unit (uptr);
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}
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