mirror of
https://github.com/rcornwell/sims.git
synced 2026-01-21 18:15:04 +00:00
IBM360: Misc changes to get system working better.
Cleaned up channel handling to properly buffer words.
End of file handling on DASD records.
Added instruction tracing to debug log.
This commit is contained in:
Richard Cornwell
parent
8cb1a59be4
commit
082a83d0ed
@ -141,6 +141,10 @@ find_subchan(uint16 device) {
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return ((device - subchannels)>>4) & 0xf;
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}
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/* Read a full word into memory.
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* Return 1 if fail.
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* Return 0 if success.
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*/
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int
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readfull(int chan, uint32 addr, uint32 *word) {
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int sk, k;
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@ -166,27 +170,94 @@ readfull(int chan, uint32 addr, uint32 *word) {
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return 0;
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}
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int writefull(int chan, uint32 addr, uint32 *word) {
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/* Read a word into the channel buffer.
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* Return 1 if fail.
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* Return 0 if success.
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*/
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int
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readbuff(int chan) {
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int sk, k;
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uint32 addr = ccw_addr[chan];
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if ((addr & AMASK) > MEMSIZE) {
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chan_status[chan] |= STATUS_PCHK;
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chan_byte[chan] = BUFF_CHNEND;
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irq_pend = 1;
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return 1;
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}
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sk = (addr >> 24) & 0xff;
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if (sk != 0) {
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if ((cpu_dev.flags & PROTECT) == 0) {
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chan_status[chan] |= STATUS_PROT;
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chan_byte[chan] = BUFF_CHNEND;
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irq_pend = 1;
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return 1;
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}
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k = key[(addr & 0xfffc00) >> 10];
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if ((k & 0x8) != 0 && (k & 0xf0) != sk) {
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chan_status[chan] |= STATUS_PROT;
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chan_byte[chan] = BUFF_CHNEND;
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irq_pend = 1;
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return 1;
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}
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}
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addr &= AMASK;
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addr >>= 2;
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M[addr] = *word;
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chan_buf[chan] = M[addr];
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sim_debug(DEBUG_DATA, &cpu_dev, "Channel write %02x %06x %08x %08x '",
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chan, ccw_addr[chan] & 0xFFFFFC, chan_buf[chan], ccw_count[chan]);
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for(k = 24; k >= 0; k -= 8) {
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char ch = ebcdic_to_ascii[(chan_buf[chan] >> k) & 0xFF];
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if (ch < 0x20 || ch == 0xff)
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ch = '.';
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sim_debug(DEBUG_DATA, &cpu_dev, "%c", ch);
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}
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sim_debug(DEBUG_DATA, & cpu_dev, "'\n");
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return 0;
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}
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/* Write channel buffer to memory.
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* Return 1 if fail.
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* Return 0 if success.
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*/
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int
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writebuff(int chan) {
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int sk, k;
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uint32 addr = ccw_addr[chan];
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if ((addr & AMASK) > MEMSIZE) {
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chan_status[chan] |= STATUS_PCHK;
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chan_byte[chan] = BUFF_CHNEND;
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irq_pend = 1;
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return 1;
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}
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sk = (addr >> 24) & 0xff;
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if (sk != 0) {
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if ((cpu_dev.flags & PROTECT) == 0) {
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chan_status[chan] |= STATUS_PROT;
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chan_byte[chan] = BUFF_CHNEND;
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irq_pend = 1;
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return 1;
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}
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k = key[(addr & 0xfffc00) >> 10];
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if ((k & 0x8) != 0 && (k & 0xf0) != sk) {
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chan_status[chan] |= STATUS_PROT;
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chan_byte[chan] = BUFF_CHNEND;
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irq_pend = 1;
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return 1;
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}
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}
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addr &= AMASK;
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addr >>= 2;
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M[addr] = chan_buf[chan];
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sim_debug(DEBUG_DATA, &cpu_dev, "Channel readf %02x %06x %08x %08x '",
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chan, ccw_addr[chan] & 0xFFFFFC, chan_buf[chan], ccw_count[chan]);
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for(k = 24; k >= 0; k -= 8) {
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char ch = ebcdic_to_ascii[(chan_buf[chan] >> k) & 0xFF];
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if (ch < 0x20 || ch == 0xff)
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ch = '.';
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sim_debug(DEBUG_DATA, &cpu_dev, "%c", ch);
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}
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sim_debug(DEBUG_DATA, &cpu_dev, "'\n");
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return 0;
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}
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@ -314,21 +385,8 @@ chan_read_byte(uint16 addr, uint8 *data) {
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}
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}
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if (chan_byte[chan] == BUFF_EMPTY) {
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if (readfull(chan, ccw_addr[chan], &chan_buf[chan])) {
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chan_byte[chan] = BUFF_CHNEND;
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irq_pend = 1;
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if (readbuff(chan))
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return 1;
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}
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sim_debug(DEBUG_DATA, &cpu_dev, "Channel write %02x %06x %08x %08x '",
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chan, ccw_addr[chan], chan_buf[chan], ccw_count[chan]);
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for(k = 24; k >= 0; k -= 8) {
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char ch = ebcdic_to_ascii[(chan_buf[chan] >> k) & 0xFF];
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if (ch < 0x20 || ch == 0xff)
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ch = '.';
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sim_debug(DEBUG_DATA, &cpu_dev, "%c", ch);
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}
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sim_debug(DEBUG_DATA, & cpu_dev, "'\n");
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chan_byte[chan] = ccw_addr[chan] & 0x3;
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ccw_addr[chan] += 4 - chan_byte[chan];
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}
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@ -356,12 +414,16 @@ chan_write_byte(uint16 addr, uint8 *data) {
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if ((ccw_cmd[chan] & 0x1) != 0) {
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return 1;
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}
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if (chan_byte[chan] == BUFF_CHNEND) {
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if ((ccw_flags[chan] & FLAG_SLI) == 0) {
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chan_status[chan] |= STATUS_LENGTH;
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}
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return 1;
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}
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if (ccw_count[chan] == 0) {
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if (chan_byte[chan] != BUFF_CHNEND) {
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if (writefull(chan, ccw_addr[chan], &chan_buf[chan])) {
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chan_byte[chan] = BUFF_CHNEND;
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if (chan_byte[chan] & BUFF_DIRTY) {
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if (writebuff(chan))
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return 1;
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}
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}
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if ((ccw_flags[chan] & FLAG_CD) == 0) {
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chan_byte[chan] = BUFF_CHNEND;
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@ -375,42 +437,18 @@ chan_write_byte(uint16 addr, uint8 *data) {
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if (load_ccw(chan, 1))
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return 1;
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}
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if (chan_byte[chan] == BUFF_CHNEND) {
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if ((ccw_flags[chan] & FLAG_SLI) == 0) {
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chan_status[chan] |= STATUS_LENGTH;
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}
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return 1;
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}
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if (ccw_flags[chan] & FLAG_SKIP) {
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ccw_count[chan]--;
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chan_byte[chan] = BUFF_EMPTY;
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if ((ccw_cmd[chan] & 0xf) == CMD_RDBWD)
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ccw_addr[chan]--;
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else
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ccw_addr[chan]++;
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// if (ccw_count[chan] == 0) {
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// if (ccw_flags[chan] & FLAG_CD)
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// return load_ccw(chan, 1);
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// else
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// chan_byte[chan] = BUFF_CHNEND;
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// return 1;
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// }
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return 0;
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}
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if (chan_byte[chan] == (BUFF_EMPTY|BUFF_DIRTY)) {
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if (writefull(chan, ccw_addr[chan], &chan_buf[chan])) {
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chan_byte[chan] = BUFF_CHNEND;
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irq_pend = 1;
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if (writebuff(chan))
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return 1;
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}
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sim_debug(DEBUG_DATA, &cpu_dev, "Channel read %02x %06x %08x %08x '",
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chan, ccw_addr[chan], chan_buf[chan], ccw_count[chan]);
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for(k = 24; k >= 0; k -= 8) {
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char ch = ebcdic_to_ascii[(chan_buf[chan] >> k) & 0xFF];
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if (ch < 0x20 || ch == 0xff)
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ch = '.';
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sim_debug(DEBUG_DATA, &cpu_dev, "%c", ch);
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}
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sim_debug(DEBUG_DATA, &cpu_dev, "'\n");
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if ((ccw_cmd[chan] & 0xf) == CMD_RDBWD)
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ccw_addr[chan] -= 1 + (ccw_addr[chan] & 0x3);
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else
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@ -418,11 +456,8 @@ chan_write_byte(uint16 addr, uint8 *data) {
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chan_byte[chan] = BUFF_EMPTY;
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}
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if (chan_byte[chan] == BUFF_EMPTY) {
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if (readfull(chan, ccw_addr[chan], &chan_buf[chan])) {
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chan_byte[chan] = BUFF_CHNEND;
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irq_pend = 1;
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if (readbuff(chan))
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return 1;
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}
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chan_byte[chan] = ccw_addr[chan] & 0x3;
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}
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ccw_count[chan]--;
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@ -464,21 +499,12 @@ chan_end(uint16 addr, uint8 flags) {
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if (chan < 0)
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return;
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if (chan_byte[chan] & BUFF_DIRTY) {
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int k;
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writefull(chan, ccw_addr[chan], &chan_buf[chan]);
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chan_byte[chan] = BUFF_EMPTY;
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sim_debug(DEBUG_DATA, &cpu_dev, "Channel read %02x %06x %08x %08x '",
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chan, ccw_addr[chan], chan_buf[chan], ccw_count[chan]);
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for(k = 24; k >= 0; k -= 8) {
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char ch = ebcdic_to_ascii[(chan_buf[chan] >> k) & 0xFF];
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if (ch < 0x20 || ch == 0xff)
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ch = '.';
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sim_debug(DEBUG_DATA, &cpu_dev, "%c", ch);
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}
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sim_debug(DEBUG_DATA, &cpu_dev, "'\n");
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}
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sim_debug(DEBUG_DETAIL, &cpu_dev, "chan_end(%x, %x) %x\n", addr, flags, ccw_count[chan]);
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if (chan_byte[chan] & BUFF_DIRTY) {
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if (writebuff(chan))
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return;
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chan_byte[chan] = BUFF_EMPTY;
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}
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chan_status[chan] |= STATUS_CEND;
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chan_status[chan] |= ((uint16)flags) << 8;
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ccw_cmd[chan] = 0;
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@ -494,15 +520,15 @@ chan_end(uint16 addr, uint8 flags) {
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if (chan_status[chan] & (STATUS_DEND|STATUS_CEND)) {
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chan_byte[chan] = BUFF_NEWCMD;
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while ((ccw_flags[chan] & FLAG_CD)) {
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while ((ccw_flags[chan] & FLAG_CD)) {
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if (load_ccw(chan, 1))
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break;
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if (ccw_count[chan] != 0 && (ccw_flags[chan] & FLAG_SLI) == 0) {
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if ((ccw_flags[chan] & FLAG_SLI) == 0) {
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sim_debug(DEBUG_DETAIL, &cpu_dev, "chan_end length\n");
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chan_status[chan] |= STATUS_LENGTH;
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ccw_flags[chan] = 0;
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}
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}
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}
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}
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irq_pend = 1;
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@ -629,10 +655,6 @@ int haltio(uint16 addr) {
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}
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if (dibp->halt_io != NULL)
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chan_status[chan] = dibp->halt_io(uptr) << 8;
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// if (chan_status[chan] & (STATUS_ATTN|STATUS_PCI|STATUS_EXPT|STATUS_CHECK|
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// STATUS_PROT|STATUS_CDATA|STATUS_CCNTL|STATUS_INTER|
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// STATUS_CHAIN))
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// return 0;
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return 0;
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}
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@ -351,9 +351,10 @@ int WriteFull(uint32 addr, uint32 data) {
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return 1;
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}
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// if ((addr & 0xfffff0) == 0xc90 && data == 0x40404040) {
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// fprintf(stderr, "Error word\n\r");
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// }
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sim_debug(DEBUG_INST, &cpu_dev, "wr fu %08x %08x ", addr, data);
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if ((addr & 0xfffffc) == 0x03c80) {
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fprintf(stderr, "Error word\n\r");
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}
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offset = addr & 0x3;
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addr >>= 2;
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@ -420,7 +421,8 @@ int WriteByte(uint32 addr, uint32 data) {
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storepsw(OPPSW, IRC_ADDR);
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return 1;
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}
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if ((addr & 0xfffff0) == 0xc90 && data == 0x40) {
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sim_debug(DEBUG_INST, &cpu_dev, "wr by %08x %02x ", addr, data);
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if ((addr & 0xfffffc) == 0x03c80) {
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fprintf(stderr, "Error byte\n\r");
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}
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@ -462,9 +464,10 @@ int WriteHalf(uint32 addr, uint32 data) {
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return 1;
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}
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// if ((addr & 0xfffff0) == 0xc90 && data == 0x4040) {
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// fprintf(stderr, "Error half\n\r");
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// }
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sim_debug(DEBUG_INST, &cpu_dev, "wr hf %08x %04x ", addr, data);
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if ((addr & 0xfffffc) == 0x03c80) {
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fprintf(stderr, "Error half\n\r");
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}
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offset = addr & 0x3;
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addr >>= 2;
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@ -607,6 +610,8 @@ wait_loop:
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ilc = 1;
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if (hst_lnt)
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hst[hst_p].inst[0] = src1;
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if ((PC & 0xFFFFF0) != 0xBA0)
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sim_debug(DEBUG_INST, &cpu_dev, "%08x %04x ", PC, src1 & 0xFFFF);
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PC += 2;
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pmsk &= ~ILMASK;
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reg = (uint8)(src1 & 0xff);
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@ -622,6 +627,8 @@ wait_loop:
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PC += 2;
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if (hst_lnt)
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hst[hst_p].inst[1] = addr1;
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if ((PC & 0xFFFFF0) != 0xBA0)
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sim_debug(DEBUG_INST, &cpu_dev, "%04x ", addr1 & 0xFFFF);
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/* Check if SS */
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if ((op & 0xc0) == 0xc0) {
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pmsk += 0x40;
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@ -631,9 +638,13 @@ wait_loop:
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ilc = 3;
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if (hst_lnt)
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hst[hst_p].inst[2] = addr2;
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if ((PC & 0xFFFFF0) != 0xBA0)
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sim_debug(DEBUG_INST, &cpu_dev, "%04x ", addr2 & 0xFFFF);
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}
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}
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if ((PC & 0xFFFFF0) != 0xBA0)
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sim_debug(DEBUG_INST, &cpu_dev, " -> ");
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/* Add in history here */
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opr:
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if (op & 0xc0) {
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@ -716,6 +727,8 @@ opr:
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hst[hst_p].src2 = src2;
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}
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if ((PC & 0xFFFFF0) != 0xBA0)
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sim_debug(DEBUG_INST, &cpu_dev, "%08x %08x - %08x %08x\n", addr1, addr2, src1, src2);
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/* Preform opcode */
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switch (op) {
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case OP_SPM:
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@ -1382,6 +1395,8 @@ save_dbl:
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} else {
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dest = src1;
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}
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if ((PC & 0xFFFFF0) != 0xBA0)
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sim_debug(DEBUG_INST, &cpu_dev, "%02x ", dest);
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//fprintf(stderr, " %x -> %x", src1, dest);
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if (WriteByte(addr1, dest))
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break;
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@ -1390,6 +1405,7 @@ save_dbl:
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reg--;
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} while (reg != 0xff);
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//fprintf(stderr, "\n\r");
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sim_debug(DEBUG_INST, &cpu_dev, "\n");
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break;
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case OP_CLC:
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@ -1990,6 +2006,13 @@ save_dbl:
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hst[hst_p].cc = cc;
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}
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if ((PC & 0xFFFFF0) != 0xBA0) {
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sim_debug(DEBUG_INST, &cpu_dev, "R0=%08x R1=%08x R2=%08x R3=%08x ", regs[0], regs[1], regs[2], regs[3]);
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sim_debug(DEBUG_INST, &cpu_dev, "R4=%08x R5=%08x R6=%08x R7=%08x\n", regs[4], regs[5], regs[6], regs[7]);
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sim_debug(DEBUG_INST, &cpu_dev, "R8=%08x R9=%08x RA=%08x RB=%08x ", regs[8], regs[9], regs[10], regs[11]);
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sim_debug(DEBUG_INST, &cpu_dev, "RC=%08x RD=%08x RE=%08x RF=%08x\n", regs[12], regs[13], regs[14], regs[15]);
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}
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if (irqaddr != 0) {
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supress:
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src1 = M[irqaddr>>2];
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@ -1007,7 +1007,7 @@ index:
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case DK_RD_CKD: /* Read count, key and data */
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/* Wait for any count */
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if (count == 0 && state == DK_POS_CNT) {
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if (count == 0 && state == DK_POS_CNT && data->rec != 0) {
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uptr->u3 |= DK_PARAM;
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uptr->u3 &= ~DK_INDEX;
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sim_debug(DEBUG_DETAIL, dptr, "RD CKD unit=%d %d k=%d d=%d %02x %04x\n",
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@ -1040,9 +1040,9 @@ index:
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rd:
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if (uptr->u3 & DK_PARAM) {
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/* Check for end of file */
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if (state == DK_POS_DATA && count == 0 && data->dlen == 0) {
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sim_debug(DEBUG_DETAIL, dptr, "RD EOF unit=%d %x %d %d\n",
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unit, state, count, data->rec);
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if (state == DK_POS_DATA && data->dlen == 0) {
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sim_debug(DEBUG_DETAIL, dptr, "RD EOF unit=%d %x %d %d d=%d\n",
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unit, state, count, data->rec, data->dlen);
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uptr->u3 &= ~(0xff|DK_PARAM);
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chan_end(addr, SNS_CHNEND|SNS_DEVEND|SNS_UNITEXP);
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break;
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@ -1230,6 +1230,14 @@ wrckd:
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uptr->u3 &= ~(0xff|DK_PARAM);
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chan_end(addr, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
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break;
|
||||
} else if ((cmd == DK_WR_KD || cmd == DK_WR_D) && state == DK_POS_DATA
|
||||
&& data->dlen == 0) {
|
||||
sim_debug(DEBUG_DETAIL, dptr, "WR EOF unit=%d %x %d %d d=%d\n",
|
||||
unit, state, count, data->rec, data->dlen);
|
||||
uptr->u3 &= ~(0xff|DK_PARAM);
|
||||
uptr->u6 = cmd;
|
||||
chan_end(addr, SNS_CHNEND|SNS_DEVEND|SNS_UNITEXP);
|
||||
break;
|
||||
} else if (state == DK_POS_DATA && data->count == data->dlen) {
|
||||
uptr->u6 = cmd;
|
||||
uptr->u3 &= ~(0xff|DK_PARAM);
|
||||
|
||||
@ -85,6 +85,7 @@ DEBTAB dev_debug[] = {
|
||||
{"DETAIL", DEBUG_DETAIL, "Show details about device"},
|
||||
{"EXP", DEBUG_EXP, "Show exception information"},
|
||||
{"POS", DEBUG_POS, "Dasd positioning information"},
|
||||
{"INST", DEBUG_INST, "Show instruction execution"},
|
||||
{0, 0}
|
||||
};
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user