github.com/rcornwell.sims
1
0
Fork 0
mirror of https://github.com/rcornwell/sims.git synced 2026-04-09 14:33:40 +00:00
Code Releases Activity

SIM32: Change instruction processing based on Gould diags.

Browse Source 
SIM32: Add more changes for UTX install tape processing.
This commit is contained in:
AZBevier
2019-08-09 19:17:55 -07:00
parent caa3398164
commit 0c3385304d
7 changed files with 455 additions and 425 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
SEL32/sel32_chan.c
View File

@@ -348,13 +348,13 @@ int writebuff(CHANP *chp)
if ((addr & MASK24) > (MEMSIZE*4)) {
chp->chan_status |= STATUS_PCHK;
sim_debug(DEBUG_EXP, &cpu_dev, "writebuff PCHK addr %x to big mem %x status %x\n", addr, MEMSIZE, chp->chan_status);
sim_debug(DEBUG_DETAIL, &cpu_dev, "writebuff PCHK addr %x to big mem %x status %x\n", addr, MEMSIZE, chp->chan_status);
chp->chan_byte = BUFF_CHNEND;
irq_pend = 1;
return 1;
}
addr &= MASK24;
sim_debug(DEBUG_EXP, &cpu_dev, "writebuff WRITE addr %x MEMSIZE %x status %x\n", addr, MEMSIZE, chp->chan_status);
sim_debug(DEBUG_DETAIL, &cpu_dev, "writebuff WRITE addr %x MEMSIZE %x status %x\n", addr, MEMSIZE, chp->chan_status);
M[addr>>2] = chp->chan_buf;
return 0;
}
@@ -454,6 +454,8 @@ loop:
/* the INCH buffer will be returned in uptr->u4 and uptr->us9 will be non-zero */
/* it should just return SNS_CHNEND and SNS_DEVEND status */
/*052619*/ chp->chan_inch_addr = uptr->u4; /* save INCH buffer address */
sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw INCH buffer save %x chan %0x status %.8x count %x\n",
uptr->u4, chan, chp->chan_status, chp->ccw_count);
}
sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw before start_cmd chan %0x status %.8x count %x\n",
@@ -705,7 +707,8 @@ void chan_end(uint16 chsa, uint16 flags) {
chp->chan_status |= ((uint16)flags); /* add in the callers flags */
// chp->ccw_cmd = 0; /* reset the completed channel command */
sim_debug(DEBUG_EXP, &cpu_dev, "chan_end SLI test chsa %x ccw_flags %x count %x status %x\n", chsa, chp->ccw_flags, chp->ccw_count, chp->chan_status);
sim_debug(DEBUG_EXP, &cpu_dev, "chan_end SLI test chsa %x ccw_flags %x count %x status %x\n",
chsa, chp->ccw_flags, chp->ccw_count, chp->chan_status);
#ifdef HACK_HACK
/* hack - rewind had byte count of 1, so triggered this error when it is not */
/* remove until I figure out what is required */
@@ -969,6 +972,8 @@ t_stat testxio(uint16 lchsa, uint32 *status) { /* test XIO */
/* nothing going on, so say all OK */
*status = CC1BIT; /* request accepted, no status, so CC1 */
tioret:
// fprintf(stderr, "$$$ TIO END chsa %x chan %x cmd %x flags %x chan_stat %x CCs %x\n",
// chsa, chan, chp->ccw_cmd, chp->ccw_flags, chp->chan_status, *status);
sim_debug(DEBUG_CMD, &cpu_dev, "$$$ TIO END chsa %x chan %x cmd %x flags %x chan_stat %x CCs %x\n",
chsa, chan, chp->ccw_cmd, chp->ccw_flags, chp->chan_status, *status);
return SCPE_OK; /* No CC's all OK */
@@ -1259,7 +1264,7 @@ uint32 scan_chan(void) {
uint32 chan; /* channel num 0-7f */
uint32 tempa; /* icb address */
uint32 chan_ivl; /* int level table address */
int lev; /* interrupt level */
// int lev; /* interrupt level */
uint32 chan_icba; /* int level context block address */
CHANP *chp; /* channel prog pointer */
DIB *dibp; /* DIB pointer */

48
SEL32/sel32_clk.c
View File

@@ -112,19 +112,8 @@ t_stat rtc_srv (UNIT *uptr)
{
if (rtc_pie) { /* set pulse intr */
INTS[rtc_lvl] |= INTS_REQ; /* request the interrupt */
//fprintf(stderr, "Clock on tic il %x act %x req %x\n", rtc_lvl, INTS[rtc_lvl] & INTS_ACT, INTS[rtc_lvl] & INTS_REQ);
irq_pend = 1; /* make sure we scan for int */
}
else {
#ifdef FIX_CLOCK_ACTIVE
if (INTS[rtc_lvl] & INTS_ACT) { /* is level active? */
INTS[rtc_lvl] &= ~INTS_ACT; /* deactivate specified int level */
SPAD[rtc_lvl+0x80] &= ~SINT_ACT; /* deactivate in SPAD too */
}
#endif
// if ((INTS[rtc_lvl] & INTS_ACT) && (INTS[rtc_lvl] & INTS_REQ)) /* is level active & requesting ? */
//fprintf(stderr, "Clock off tic il %x act %x req %x\n", rtc_lvl, INTS[rtc_lvl] & INTS_ACT, INTS[rtc_lvl] & INTS_REQ);
}
rtc_unit.wait = sim_rtcn_calb (rtc_tps, TMR_RTC); /* calibrate */
sim_activate_after (&rtc_unit, 1000000/rtc_tps);/* reactivate 16666 tics / sec */
return SCPE_OK;
@@ -142,20 +131,10 @@ void rtc_setup(uint32 ss, uint32 level)
rtc_lvl = level; /* save the interrupt level */
addr = M[addr>>2]; /* get the interrupt context block addr */
if (ss == 1) { /* starting? */
// fprintf(stderr, "Clock start pie %x act = %x req %x\n", rtc_pie, INTS[rtc_lvl] & INTS_ACT, INTS[rtc_lvl] & INTS_REQ);
INTS[level] |= INTS_ENAB; /* make sure enabled */
SPAD[level+0x80] |= SINT_ENAB; /* in spad too */
sim_activate(&rtc_unit, 20); /* start us off */
} else {
// fprintf(stderr, "Clock stop pie %x act = %x req %x\n", rtc_pie, INTS[rtc_lvl] & INTS_ACT, INTS[rtc_lvl] & INTS_REQ);
#ifdef FIX_CLOCK_ACTIVE
if ((rtc_pie == 0) && (INTS[rtc_lvl] & INTS_ACT)) { /* is level active & requesting ? */
/* should still not be busy, so maybe diags running */
//fprintf(stderr, "Clock already stopped, do DAI act = %x req %x\n", INTS[rtc_lvl] & INTS_ACT, INTS[rtc_lvl] & INTS_REQ);
INTS[rtc_lvl] &= ~INTS_ACT; /* deactivate specified int level */
SPAD[rtc_lvl+0x80] &= ~SINT_ACT; /* deactivate in SPAD too */
}
#endif
INTS[level] &= ~INTS_ENAB; /* make sure disabled */
SPAD[level+0x80] &= ~SINT_ENAB; /* in spad too */
}
@@ -166,7 +145,6 @@ void rtc_setup(uint32 ss, uint32 level)
t_stat rtc_reset(DEVICE *dptr)
{
rtc_pie = 0; /* disable pulse */
//MARKFIX rtc_unit.wait = sim_rtcn_init(rtc_unit.wait, TMR_RTC); /* initialize clock calibration */
rtc_unit.wait = sim_rtcn_init_unit(&rtc_unit, rtc_unit.wait, TMR_RTC); /* initialize clock calibration */
sim_activate (&rtc_unit, rtc_unit.wait); /* activate unit */
return SCPE_OK;
@@ -216,6 +194,8 @@ const char *rtc_desc(DEVICE *dptr)
/* Interval Timer support */
int32 itm_pie = 0; /* itm pulse enable */
int32 itm_cmd = 0; /* itm last user cmd */
int32 itm_cnt = 0; /* itm pulse count enable */
int32 itm_tick_size_x_100 = 3840; /* itm 26041 ticks/sec = 38.4 us per tic */
int32 itm_lvl = 0x5f; /* itm interrupt level */
t_stat itm_srv (UNIT *uptr);
@@ -236,6 +216,8 @@ UNIT itm_unit = { UDATA (&itm_srv, UNIT_IDLE, 0), 26042, UNIT_ADDR(0x7F04)};
REG itm_reg[] = {
{ FLDATA (PIE, itm_pie, 0) },
{ FLDATA (CNT, itm_cnt, 0) },
{ FLDATA (CMD, itm_cmd, 0) },
{ DRDATA (TICK_SIZE, itm_tick_size_x_100, 32), PV_LEFT + REG_HRO },
{ NULL }
};
@@ -273,13 +255,19 @@ t_stat itm_srv (UNIT *uptr)
if (itm_pie) { /* interrupt enabled? */
INTS[itm_lvl] |= INTS_REQ; /* request the interrupt on zero value */
irq_pend = 1; /* make sure we scan for int */
if (itm_cmd == 0x3d) {
/* restart timer with value from user */
sim_activate_after_abs_d (&itm_unit, ((double)itm_cnt * itm_tick_size_x_100) / 100.0);
}
}
return SCPE_OK;
}
/* ITM read/load function called from CD command processing */
/* level = interrupt level */
/* cmd = 0x39 load and enable interval timer, no return value */
/* cmd = 0x20 stop timer, do not transfer any value */
/* = 0x39 load and enable interval timer, no return value */
/* = 0x3d load and enable interval timer, countdown to zero, interrupt and reload */
/* = 0x40 read timer value */
/* = 0x60 read timer value and stop timer */
/* = 0x79 read/reload and start timer */
@@ -288,12 +276,25 @@ t_stat itm_srv (UNIT *uptr)
int32 itm_rdwr(uint32 cmd, int32 cnt, uint32 level)
{
uint32 temp;
itm_cmd = cmd; /* save last cmd */
switch (cmd) {
case 0x20: /* stop timer */
sim_cancel (&itm_unit); /* cancel itc */
itm_cnt = 0; /* no count reset value */
return 0; /* does not matter, no value returned */
case 0x39: /* load timer with new value and start*/
if (cnt < 0)
cnt = 26042; /* TRY ??*/
/* start timer with value from user */
sim_activate_after_abs_d (&itm_unit, ((double)cnt * itm_tick_size_x_100) / 100.0);
sim_cancel (&itm_unit);
itm_cnt = 0; /* no count reset value */
return 0; /* does not matter, no value returned */
case 0x3d: /* load timer with new value and start*/
/* start timer with value from user, reload on zero time */
sim_activate_after_abs_d (&itm_unit, ((double)cnt * itm_tick_size_x_100) / 100.0);
itm_cnt = cnt; /* count reset value */
return 0; /* does not matter, no value returned */
case 0x60: /* read and stop timer */
/* get timer value and stop timer */
@@ -305,6 +306,7 @@ int32 itm_rdwr(uint32 cmd, int32 cnt, uint32 level)
temp = (uint32)(100.0 * sim_activate_time_usecs (&itm_unit) / itm_tick_size_x_100);
/* start timer to fire after cnt ticks */
sim_activate_after_abs_d (&itm_unit, ((double)cnt * itm_tick_size_x_100) / 100.0);
itm_cnt = 0; /* no count reset value */
return temp; /* return current count value */
case 0x40: /* read the current timer value */
/* return current count value */

790
SEL32/sel32_cpu.c
View File

File diff suppressed because it is too large Load Diff

1
SEL32/sel32_defs.h
View File

@@ -322,6 +322,7 @@ extern DEBTAB dev_debug[];
#define MAPFLT MAPFAULT_TRAP /* map fault error */
#define NPMEM NONPRESMEM_TRAP /* non present memory */
#define MPVIOL PRIVVIOL_TRAP /* memory protection violation */
#define DMDPG DEMANDPG_TRAP /* Demand Page Fault Trap (V6&V9 Only) */
/* general instruction decode equates */
#define IND 0x00100000 /* indirect bit in instruction, bit 11 */

15
SEL32/sel32_disk.c
View File

@@ -434,11 +434,10 @@ uint8 disk_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
if ((uptr->CMD & 0xff00) != 0) { /* if any status info, we are busy */
return SNS_BSY;
}
sim_debug(DEBUG_CMD, dptr, "disk_startcmd CMD continue unit=%d %02x\n", unit, cmd);
sim_debug(DEBUG_CMD, dptr, "disk_startcmd CMD continue unit=%d cmd %02x\n", unit, cmd);
if ((uptr->flags & UNIT_ATT) == 0) { /* see if unit is attached */
if (cmd == DSK_SNS) { /* not attached, is cmd Sense 0x04 */
dosns:
sim_debug(DEBUG_CMD, dptr, "disk_startcmd CMD sense\n");
/* bytes 0,1 - Cyl entry from STAR reg in STAR */
ch = (uptr->STAR >> 24) & 0xff;
@@ -512,7 +511,7 @@ dosns:
UNIT *up = dptr->units; /* first unit for this device */
sim_debug(DEBUG_CMD, dptr, "disk_startcmd starting inch cmd addr %x STAR %x\n",
addr, uptr->STAR);
/* STAR has IOCD word 1 contents. For the disk processor it contains */
/* STAR (u4) has IOCD word 1 contents. For the disk processor it contains */
/* a pointer to the INCH buffer followed by 8 drive attribute words that */
/* contains the flags, sector count, MHD head count, and FHD count */
/* us9 has the byte count from IOCD wd2 and should be 0x24 (36) */
@@ -528,6 +527,8 @@ dosns:
/* so we will not have a map fault */
for (i=0; i<dptr->numunits && i<8; i++) { /* process all drives */
up->ATTR = M[(mema>>2)+i+1]; /* save each unit's drive data */
sim_debug(DEBUG_CMD, dptr, "disk_startcmd ATTR data %x flags %x sec %x MHD %x FHD %x\n",
up->ATTR, i, (up->ATTR >> 24)&0xff, (up->ATTR >> 16)&0xff, (up->ATTR >> 8)&0xff, (up->ATTR&0xff));
up++; /* next unit for this device */
}
sim_debug(DEBUG_CMD, dptr, "disk_startcmd done inch cmd addr %x\n", addr);
@@ -662,7 +663,7 @@ t_stat disk_srv(UNIT * uptr)
data->cyl++; /* Seek 1 cyl */
sim_activate(uptr, 200);
}
if (data->cyl >= disk_type[type].cyl) /* test for over max */
if (data->cyl >= (int)disk_type[type].cyl) /* test for over max */
data->cyl = disk_type[type].cyl-1; /* make max */
} else {
if (i < -50) {
@@ -845,7 +846,7 @@ rezero:
if (data->tpos >= (disk_type[type].nhds)) {
data->tpos = 0; /* number of tracks per cylinder */
data->cyl++; /* cylinder position */
if (data->cyl >= (disk_type[type].cyl)) {
if (data->cyl >= (int)(disk_type[type].cyl)) {
/* EOM reached, abort */
uptr->CMD &= ~(0xffff); /* remove old status bits & cmd */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
@@ -924,7 +925,7 @@ rddone:
if (data->tpos >= (disk_type[type].nhds)) {
data->tpos = 0; /* number of tracks per cylinder */
data->cyl++; /* cylinder position */
if (data->cyl >= (disk_type[type].cyl)) {
if (data->cyl >= (int)(disk_type[type].cyl)) {
/* EOM reached, abort */
sim_debug(DEBUG_DETAIL, dptr,
"Error %d on write %d to diskfile cyl %d hds %d sec %d\n",
@@ -984,7 +985,7 @@ t_stat disk_attach(UNIT *uptr, CONST char *file)
uint16 tsize; /* track size in bytes */
uint16 ssize; /* sector size in bytes */
struct ddata_t *data;
uint8 buff[1024];
// uint8 buff[1024];
/* have simulator attach the file to the unit */
if ((r = attach_unit(uptr, file)) != SCPE_OK)

10
SEL32/sel32_scfi.c
View File

@@ -80,6 +80,7 @@ bits 24-31 - FHD head count (number of heads on FHD or number head on FHD option
/* 26 words of scratchpad */
/* 4 words of label buffer registers */
#define CMD u3
/* u3 */
/* in u3 is device command code and status */
#define DSK_CMDMSK 0x00ff /* Command being run */
@@ -117,12 +118,14 @@ bits 24-31 - FHD head count (number of heads on FHD or number head on FHD option
#define DSK_TESS 0xAB /* Test STAR (subchannel target address register) */
#define DSK_ICH 0xFF /* Initialize Controller */
#define STAR u4
/* u4 - sector target address register (STAR) */
/* Holds the current cylinder, head(track), sector */
#define DISK_CYL 0xFFFF0000 /* cylinder mask */
#define DISK_TRACK 0x0000FF00 /* track mask */
#define DISK_SECTOR 0x000000ff /* sector mask */
#define SNS u5
/* u5 */
/* Sense byte 0 - mode register */
#define SNS_DROFF 0x80000000 /* Drive Carriage will be offset */
@@ -164,6 +167,7 @@ bits 24-31 - FHD head count (number of heads on FHD or number head on FHD option
#define SNS_RTAE 0x02 /* Reserve track access error */
#define SNS_UESS 0x01 /* Uncorrectable ECC error */
#define ATTR u6
/* u6 */
/* u6 holds drive attribute entry */
/* provided by inch command for controller */
@@ -181,6 +185,7 @@ bits 16-23 - MHD Head count (number of heads on MHD)
bits 24-31 - FHD head count (number of heads on FHD or number head on FHD option of mini-module)
*/
#define DDATA up7
/* Pointer held in up7 */
/* sects/cylinder = sects/track * numhds */
/* allocated during attach command for each unit defined */
@@ -441,11 +446,10 @@ uint8 scfi_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) {
if ((uptr->u3 & 0xff00) != 0) { /* if any status info, we are busy */
return SNS_BSY;
}
sim_debug(DEBUG_CMD, dptr, "scfi_startcmd CMD 2 unit=%d %02x\n", unit, cmd);
sim_debug(DEBUG_CMD, dptr, "scfi_startcmd CMD 2 unit=%d cmd %02x\n", unit, cmd);
if ((uptr->flags & UNIT_ATT) == 0) { /* see if unit is attached */
if (cmd == DSK_SNS) { /* not attached, is cmd Sense 0x04 */
dosns:
sim_debug(DEBUG_CMD, dptr, "scfi_startcmd CMD sense\n");
/* bytes 0,1 - Cyl entry from STAR reg in u4 */
ch = (uptr->u4 >> 24) & 0xff;
@@ -524,6 +528,8 @@ dosns:
/* so we will not have a map fault */
for (i=0; i<dptr->numunits && i<8; i++) { /* process all drives */
up->u6 = M[(mema>>2)+i+1]; /* save each unit's drive data */
sim_debug(DEBUG_CMD, dptr, "scfi_startcmd ATTR data %x flags %x sec %x MHD %x FHD %x\n",
up->ATTR, i, (up->ATTR >> 24)&0xff, (up->ATTR >> 16)&0xff, (up->ATTR >> 8)&0xff, (up->ATTR&0xff));
up++; /* next unit for this device */
}
sim_debug(DEBUG_CMD, dptr, "scfi_startcmd done inch cmd addr %x\n", addr);

3
SEL32/sel32_sys.c
View File

@@ -865,7 +865,8 @@ int fprint_inst(FILE *of, uint32 val, int32 sw)
fputc(')', of);
}
// if (inst & 0x70) {
if ((inst & 0x70) && (tab->type != TYPE_D)) {
// if ((inst & 0x70) && (tab->type != TYPE_D)) {
if (inst & 0x70) {
fputc(',', of);
// fputc('R', of);
fputc(('0'+((inst >> 4) & 07)), of); /* output the index reg number */