mirror of
https://github.com/rcornwell/sims.git
synced 2026-01-28 04:47:38 +00:00
B5500: Fixed disconneting from DTC and processor switching.
This commit is contained in:
Richard Cornwell
@@ -213,7 +213,7 @@ uint16 l_reg[2]; /* L current syllable pointer */
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uint8 ncsf_reg[2]; /* True if normal state */
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uint8 salf_reg[2]; /* True if subrogram mode */
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uint8 cwmf_reg[2]; /* True if character mode */
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uint8 hltf[2]; /* True if processor halted */
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uint16 hltf[2]; /* True if processor halted */
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uint8 msff_reg[2]; /* Mark stack flag Word mode */
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#define TFFF MSFF /* True state in Char mode */
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uint8 varf_reg[2]; /* Variant Flag */
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@@ -960,10 +960,10 @@ void storeInterrupt(int forced, int test) {
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}
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AROF = 0;
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B = ICW; /* Set ICW into B */
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next_addr(S); /* Save B */
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next_addr(S); /* Save B */
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memory_cycle(11);
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B = RCW(f); /* Save IRCW */
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next_addr(S); /* Save B */
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next_addr(S); /* Save B */
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memory_cycle(11);
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if (CWMF) {
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/* Get the correct value of R */
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@@ -1994,7 +1994,6 @@ sim_instr(void)
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if (P1_run == 0)
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return SCPE_STOP;
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while (loading) {
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sim_interval = -1;
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reason = sim_process_event();
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if (reason != SCPE_OK) {
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break; /* process */
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@@ -2027,20 +2026,15 @@ sim_instr(void)
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}
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/* Toggle between two CPU's. */
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if (TROF == 0 && NCSF) {
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if (Q != 0 || ((cpu_index)? HLTF : IAR) != 0)
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storeInterrupt(1,0);
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}
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if (cpu_index == 0 && P2_run == 1) {
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cpu_index = 1;
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/* Check if interrupt pending. */
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if (TROF == 0 && NCSF && ((Q != 0) || HLTF))
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/* Force a SFI */
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storeInterrupt(1,0);
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} else {
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cpu_index = 0;
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/* Check if interrupt pending. */
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if (TROF == 0 && NCSF && ((Q != 0) ||
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(IAR != 0)))
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/* Force a SFI */
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storeInterrupt(1,0);
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}
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if (TROF == 0)
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next_prog();
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@@ -3678,15 +3672,17 @@ control:
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R = 0;
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F = S; /* Set F and X */
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X = toF(S);
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S = CF(B);
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if (B & FLAG) {
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if ((B & PRESENT) == 0 && NCSF)
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Q |= PRES_BIT;
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else
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KV = 0;
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if ((B & PRESENT) == 0) {
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if (NCSF)
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Q |= PRES_BIT;
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break;
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}
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KV = 0;
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} else {
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KV = (uint8)((B >> (FFIELD_V - 3)) & 070);
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}
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S = CF(B);
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break;
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case VARIANT(WMOP_MKS): /* Mark Stack */
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@@ -76,6 +76,7 @@
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#define BufAbnormal 010 /* Abnornmal flag */
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#define BufGM 020 /* Buffer term with GM */
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#define BufIRQ 040 /* Buffer ready */
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#define BufDisco 0100 /* Buffer disconnecting */
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/* Not connected line:
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BufNotReady.
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@@ -350,7 +351,7 @@ t_stat dtc_srv(UNIT * uptr)
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}
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/* Process for each unit */
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if (uptr->u5 & DTC_WR) {
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if (line > dtc_desc.lines || line == -1) {
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if (line > dtc_desc.lines || line == -1 || dtc_lstatus[line] & BufDisco) {
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sim_debug(DEBUG_DETAIL, &dtc_dev, "Datacomm write invalid %d\n",
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line);
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chan_set_notrdy(chan);
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@@ -434,7 +435,7 @@ t_stat dtc_srv(UNIT * uptr)
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}
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if (uptr->u5 & DTC_RD) {
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if (line > dtc_desc.lines || line == -1) {
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if (line > dtc_desc.lines || line == -1 || dtc_lstatus[line] & BufDisco) {
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sim_debug(DEBUG_DETAIL, &dtc_dev, "Datacomm read nothing %d\n",
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line);
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chan_set_notrdy(chan);
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@@ -489,7 +490,7 @@ t_stat dtc_srv(UNIT * uptr)
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if (dtc_lstatus[line] & BufAbnormal)
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chan_set_wcflg(chan);
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if (dtc_ldsc[line].conn == 0) /* connected? */
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dtc_lstatus[line] = BufIRQ|BufNotReady;
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dtc_lstatus[line] = BufIRQ|BufAbnormal|BufIRQ|BufIdle;
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else
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dtc_lstatus[line] = BufIRQ|BufIdle;
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dtc_bsize[line] = 0;
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@@ -524,6 +525,7 @@ dtco_srv(UNIT * uptr)
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sim_clock_coschedule(uptr, tmxr_poll);
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ln = tmxr_poll_conn(&dtc_desc); /* look for connect */
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if (ln >= 0) { /* got one? */
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dtc_ldsc[ln].rcve = 1;
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dtc_blimit[ln] = dtc_bufsize-1;
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dtc_lstatus[ln] = BufIRQ|BufAbnormal|BufWriteRdy;
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IAR |= IRQ_12;
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@@ -532,32 +534,43 @@ dtco_srv(UNIT * uptr)
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/* For each line that is in idle state enable recieve */
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for (ln = 0; ln < dtc_desc.lines; ln++) {
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if (dtc_ldsc[ln].conn &&
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(dtc_lstatus[ln] & BufSMASK) == BufIdle) {
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dtc_ldsc[ln].rcve = 0;
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if (dtc_ldsc[ln].conn &&
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(dtc_lstatus[ln] & BufSMASK) < BufWrite) {
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dtc_ldsc[ln].rcve = 1;
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}
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}
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tmxr_poll_rx(&dtc_desc); /* poll for input */
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for (ln = 0; ln < DTC_MLINES; ln++) { /* loop thru mux */
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/* Check for disconnect */
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if (dtc_ldsc[ln].conn == 0) { /* connected? */
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if (dtc_ldsc[ln].conn == 0 && (dtc_lstatus[ln] & BufDisco) == 0) { /* connected? */
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dtc_ldsc[ln].rcve = 0;
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switch(dtc_lstatus[ln] & BufSMASK) {
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case BufIdle: /* Idle, throw in EOT */
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/* Fall through */
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case BufIdle: /* Idle Flag as disconnected */
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dtc_lstatus[ln] = BufIRQ|BufAbnormal|BufIdle|BufDisco;
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dtc_bsize[ln] = 0;
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IAR |= IRQ_12;
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sim_debug(DEBUG_DETAIL, &dtc_dev, "Datacomm disconnect %d idle\n", ln);
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break;
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case BufWriteRdy: /* Awaiting output, terminate */
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dtc_bufptr[ln] = 0;
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/* Fall through */
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case BufInputBusy: /* reading, terminate with EOT */
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dtc_buf[ln][dtc_bufptr[ln]++] = 017;
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dtc_bsize[ln] = dtc_bufptr[ln];
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dtc_bsize[ln] = dtc_bufptr[ln]+1;
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dtc_lstatus[ln] = BufIRQ|BufAbnormal|BufReadRdy;
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IAR |= IRQ_12;
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sim_debug(DEBUG_DETAIL, &dtc_dev, "Datacomm disconnect %d write\n", ln);
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break;
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case BufOutBusy: /* Terminate Output */
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dtc_lstatus[ln] = BufIRQ|BufIdle;
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dtc_lstatus[ln] = BufIRQ|BufIdle|BufAbnormal;
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dtc_bsize[ln] = 0;
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IAR |= IRQ_12;
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sim_debug(DEBUG_DETAIL, &dtc_dev, "Datacomm disconnect %d out\n", ln);
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break;
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default: /* Other cases, ignore until
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in better state */
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break;
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@@ -568,9 +581,10 @@ dtco_srv(UNIT * uptr)
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switch(dtc_lstatus[ln] & BufSMASK) {
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case BufIdle:
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/* If we have any data to receive */
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if (tmxr_rqln(&dtc_ldsc[ln]) > 0)
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dtc_lstatus[ln] = BufInputBusy;
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else
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if (tmxr_rqln(&dtc_ldsc[ln]) > 0) {
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dtc_lstatus[ln] &= ~(BufSMASK);
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dtc_lstatus[ln] |= BufInputBusy;
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} else
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break; /* Nothing to do */
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sim_debug(DEBUG_DETAIL, &dtc_dev, "Datacomm recieve %d idle\n",
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ln);
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@@ -580,9 +594,9 @@ dtco_srv(UNIT * uptr)
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case BufInputBusy:
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t = 1;
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while (t && tmxr_rqln(&dtc_ldsc[ln]) != 0) {
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while (t) {
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c = tmxr_getc_ln(&dtc_ldsc[ln]); /* get char */
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if ((c & TMXR_VALID) == 0)
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if (c == 0)
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break;
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c &= 0x7f;
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c1 = ascii_to_con[c];
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@@ -136,7 +136,7 @@ const char ascii_to_con[128] = {
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/* Control */
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-1, -1, -1, -1, -1, -1, -1, -1,
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/*sp ! " # $ % & ' */
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020, 032, 037, 013, 053, 017, 060, 014, /* 40 - 77 */
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020, 032, 037, 013, 053, 034, 060, 014, /* 40 - 77 */
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/* ( ) * + , - . / */
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075, 055, 054, 072, 033, 040, 073, 021,
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/* 0 1 2 3 4 5 6 7 */
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@@ -158,7 +158,7 @@ const char ascii_to_con[128] = {
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/* p q r s t u v w */
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047, 050, 051, 022, 023, 024, 025, 026,
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/* x y z { | } ~ del*/
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027, 030, 031, 057, 077, 017, -1, -1
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027, 030, 031, 057, 052, 017, -1, -1
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};
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