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KA10: Fixes fro 340 display.
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commit
2a9ecf0865
@ -117,7 +117,7 @@ extern uint64 SW; /* switch register */
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* number of DPY_CYCLES to delay int
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* too small and host CPU doesn't run enough!
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*/
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#define INT_COUNT (500/DPY_CYCLE_US)
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#define INT_COUNT (100/DPY_CYCLE_US)
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#define STAT_REG u3
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#define INT_COUNTDOWN u4
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@ -181,10 +181,23 @@ const char *dpy_description (DEVICE *dptr)
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/* until it's done just one place! */
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static void dpy_set_int_done(UNIT *uptr)
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{
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uptr->STAT_REG |= CONI_INT_DONE;
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uptr->INT_COUNTDOWN = INT_COUNT;
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}
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/* update interrupt request */
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static void check_interrupt (UNIT *uptr)
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{
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if (uptr->STAT_REG & CONI_INT_SPEC) {
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uint32 sc = uptr->STAT_REG & CONX_SC;
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set_interrupt(DPY_DEVNUM, sc >> CONX_SC_SHIFT);
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} else if (uptr->STAT_REG & CONI_INT_DONE) {
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uint32 dc = uptr->STAT_REG & CONX_DC;
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set_interrupt(DPY_DEVNUM, dc>>CONX_DC_SHIFT);
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} else {
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clr_interrupt(DPY_DEVNUM);
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}
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}
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/* return true if display not stopped */
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int dpy_update_status (UNIT *uptr, ty340word status, int done)
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{
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@ -199,12 +212,7 @@ int dpy_update_status (UNIT *uptr, ty340word status, int done)
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/* XXX also set in "rfd" callback: decide! */
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dpy_set_int_done(uptr);
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}
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if (uptr->STAT_REG & CONI_INT_SPEC) {
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uint32 sc = uptr->STAT_REG & CONX_SC;
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if (sc) { /* PI channel set? */
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set_interrupt(DPY_DEVNUM, sc >> CONX_SC_SHIFT);
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}
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}
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check_interrupt(uptr);
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return running;
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}
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@ -287,12 +295,8 @@ t_stat dpy_svc (UNIT *uptr)
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display_age(DPY_CYCLE_US, 0); /* age the display */
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if (uptr->INT_COUNTDOWN && --uptr->INT_COUNTDOWN == 0) {
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if (uptr->STAT_REG & CONI_INT_DONE) { /* delayed int? */
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uint32 dc = uptr->STAT_REG & CONX_DC;
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if (dc) { /* PI channel set? */
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set_interrupt(DPY_DEVNUM, dc>>CONX_DC_SHIFT);
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}
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}
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uptr->STAT_REG |= CONI_INT_DONE;
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check_interrupt (uptr);
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}
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return SCPE_OK;
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}
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