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mirror of https://github.com/rcornwell/sims.git synced 2026-01-19 09:28:10 +00:00

KA10: Cleanup compile errors, fix bug with terminal mux

This commit is contained in:
Richard Cornwell 2017-04-25 08:26:09 -04:00
parent 5d7fb25895
commit 4f42dd9c80
5 changed files with 33 additions and 51 deletions

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@ -3854,7 +3854,7 @@ test_op:
case 0774: case 0775: case 0776: case 0777:
#if KI
if (!pi_cycle && ((FLAGS & (USER|USERIO)) == USER) &&
(IR & 040) == 0 || ((FLAGS & (USER|PUBLIC)) == PUBLIC)) {
((IR & 040) == 0 || ((FLAGS & (USER|PUBLIC)) == PUBLIC))) {
#else
if ((FLAGS & (USER|USERIO)) == USER && !pi_cycle) {

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@ -242,7 +242,10 @@ t_stat dc_devio(uint32 dev, uint64 *data) {
int32 ch = *data & DATA;
ch = sim_tt_outcvt(ch, TT_GET_MODE (dc_unit.flags) | TTUF_KSR);
tmxr_putc_ln (lp, ch);
tx_enable |= (1 << ln);
if (lp->xmte)
tx_enable |= (1 << ln);
else
tx_enable &= ~(1 << ln);
dc_l_status |= (1LL << ln);
}
}
@ -261,9 +264,9 @@ t_stat dc_devio(uint32 dev, uint64 *data) {
if (dc_enable & (1 << ln))
*data |= FLAG|OFF_HOOK;
if (rx_conn & (1 << ln) && lp->conn)
*data |= FLAG|CTS;
*data |= FLAG|CTS;
if (dc_ring & (1 << ln))
*data |= FLAG|RES_DET;
*data |= FLAG|RES_DET;
} else if (ln < dc_desc.lines) {
/* Nothing happens if no recieve data, which is transmit ready */
lp = &dc_ldsc[ln];
@ -311,6 +314,11 @@ int32 ln;
tmxr_poll_tx(&dc_desc);
tmxr_poll_rx(&dc_desc);
for (ln = 0; ln < dc_desc.lines; ln++) {
/* Check if buffer empty */
if (dc_ldsc[ln].xmte) {
tx_enable |= dc_l_status & (1 << ln);
}
/* Check to see if any pending data for this line */
if (tmxr_rqln(&dc_ldsc[ln]) > 0) {
rx_rdy |= (1 << ln);

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@ -249,17 +249,6 @@
int32 dtsa = 0; /* status A */
t_uint64 dtsb = 0; /* status B */
t_uint64 dtdb = 0; /* data buffer */
#if 0
int32 dt_ltime = 12; /* interline time */
int32 dt_dctime = 40000; /* decel time */
int32 dt_substate = 0;
int32 dt_logblk = 0;
int32 dt_stopoffr = 0; /* stop on off reel */
static const int32 map_unit[16] = { /* Type 550 unit map */
-1, 1, 2, 3, 4, 5, 6, 7,
0, -1, -1, -1, -1, -1, -1, -1
};
#endif
t_stat dt_devio(uint32 dev, uint64 *data);
t_stat dt_svc (UNIT *uptr);
@ -267,20 +256,6 @@ t_stat dt_boot(int32 unit_num, DEVICE * dptr);
t_stat dt_reset (DEVICE *dptr);
t_stat dt_attach (UNIT *uptr, CONST char *cptr);
t_stat dt_detach (UNIT *uptr);
#if 0
int32 dt75 (int32 dev, int32 pulse, int32 dat);
int32 dt76 (int32 dev, int32 pulse, int32 dat);
int32 dt_iors (void);
void dt_deselect (int32 oldf);
void dt_newsa (int32 newf);
void dt_newfnc (UNIT *uptr, int32 newsta);
t_bool dt_setpos (UNIT *uptr);
void dt_schedez (UNIT *uptr, int32 dir);
void dt_seterr (UNIT *uptr, int32 e);
int32 dt_comobv (int32 val);
int32 dt_csum (UNIT *uptr, int32 blk);
int32 dt_gethdr (UNIT *uptr, int32 blk, int32 relpos);
#endif
/* DT data structures
@ -315,13 +290,6 @@ REG dt_reg[] = {
{ ORDATA (DTSA, dtsa, 18) },
{ ORDATA (DTSB, dtsb, 18) },
{ ORDATA (DTDB, dtdb, 18) },
#if 0
{ DRDATA (LTIME, dt_ltime, 31), REG_NZ },
{ DRDATA (DCTIME, dt_dctime, 31), REG_NZ },
{ ORDATA (SUBSTATE, dt_substate, 2) },
{ DRDATA (LBLK, dt_logblk, 12), REG_HIDDEN },
{ FLDATA (STOP_OFFR, dt_stopoffr, 0) },
#endif
{ URDATA (POS, dt_unit[0].pos, 10, T_ADDR_W, 0,
DT_NUMDR, PV_LEFT | REG_RO) },
{ NULL }
@ -510,7 +478,7 @@ t_stat dt_devio(uint32 dev, uint64 *data) {
return SCPE_OK;
}
void dt_getword(t_int64 *data, int req) {
void dt_getword(t_uint64 *data, int req) {
int dev = dt_dib.dev_num;
clr_interrupt(dev|4);
if (dtsb & DTB_DATREQ) {
@ -524,7 +492,7 @@ void dt_getword(t_int64 *data, int req) {
}
}
void dt_putword(t_int64 *data) {
void dt_putword(t_uint64 *data) {
int dev = dt_dib.dev_num;
clr_interrupt(dev|4);
if (dtsb & DTB_DATREQ) {

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@ -489,8 +489,12 @@ rs_write(int ctlr, int unit, int reg, uint32 data) {
case FNC_DCLR: /* drive clear */
uptr->u3 |= DS_DRY;
uptr->u3 &= ~(DS_ATA|CR_GO);
rs_attn[ctlr] &= ~(1<<unit);
rs_attn[ctlr] = 0;
clr_interrupt(rs_dib[ctlr].dev_num);
for (i = 0; i < 8; i++) {
if (rs_unit[(ctlr * 8) + i].u3 & DS_ATA)
rs_attn[ctlr] = 1;
}
if ((df10->status & IADR_ATTN) != 0 && rs_attn[ctlr] != 0)
df10_setirq(df10);
break;
@ -518,11 +522,12 @@ rs_write(int ctlr, int unit, int reg, uint32 data) {
case 003: /* maintenance */
break;
case 004: /* atten summary */
rs_attn[ctlr] = 0;
for (i = 0; i < 8; i++) {
if (data & (1<<i)) {
if (data & (1<<i))
rs_unit[(ctlr * 8) + i].u3 &= ~DS_ATA;
rs_attn[ctlr] &= ~(1<<i);
}
if (rs_unit[(ctlr * 8) + i].u3 & DS_ATA)
rs_attn[ctlr] = 1;
}
clr_interrupt(rs_dib[ctlr].dev_num);
if (((df10->status & IADR_ATTN) != 0 && rs_attn[ctlr] != 0) ||
@ -625,7 +630,7 @@ t_stat rs_svc (UNIT *uptr)
case FNC_DCLR: /* drive clear */
break;
case FNC_PRESET: /* read-in preset */
rs_attn[ctlr] |= 1<<unit;
rs_attn[ctlr] = 1;
uptr->u3 |= DS_DRY|DS_ATA;
uptr->u3 &= ~CR_GO;
df->status &= ~BUSY;
@ -638,7 +643,7 @@ t_stat rs_svc (UNIT *uptr)
if (GET_SC(uptr->u4) >= rs_drv_tab[dtype].sect ||
GET_SF(uptr->u4) >= rs_drv_tab[dtype].surf)
uptr->u3 |= (ER1_IAE << 16)|DS_ERR;
rs_attn[ctlr] |= 1<<unit;
rs_attn[ctlr] = 1;
uptr->u3 |= DS_DRY|DS_ATA;
uptr->u3 &= ~CR_GO;
df->status &= ~BUSY;
@ -654,7 +659,7 @@ t_stat rs_svc (UNIT *uptr)
if (GET_SC(uptr->u4) >= rs_drv_tab[dtype].sect ||
GET_SF(uptr->u4) >= rs_drv_tab[dtype].surf) {
uptr->u3 |= (ER1_IAE << 16)|DS_ERR|DS_DRY|DS_ATA;
rs_attn[ctlr] |= 1<<unit;
rs_attn[ctlr] = 1;
df->status &= ~BUSY;
uptr->u3 &= ~CR_GO;
sim_debug(DEBUG_DETAIL, dptr, "RSA%o readx done\n", unit);
@ -703,7 +708,7 @@ t_stat rs_svc (UNIT *uptr)
if (GET_SC(uptr->u4) >= rs_drv_tab[dtype].sect ||
GET_SF(uptr->u4) >= rs_drv_tab[dtype].surf) {
uptr->u3 |= (ER1_IAE << 16)|DS_ERR|DS_DRY|DS_ATA;
rs_attn[ctlr] |= 1<<unit;
rs_attn[ctlr] = 1;
df->status &= ~BUSY;
uptr->u3 &= ~CR_GO;
sim_debug(DEBUG_DETAIL, dptr, "RSA%o writex done\n", unit);

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@ -460,9 +460,9 @@ tu_devirq(uint32 dev, int addr) {
void
tu_write(int ctlr, int unit, int reg, uint32 data) {
UNIT *uptr = &tu_unit[(ctlr * 8) + (tu_tcr[ctlr] & 07)];
int i;
DEVICE *dptr = tu_devs[ctlr];
struct df10 *df10 = &tu_df10[ctlr];
int i;
if (uptr->u3 & CR_GO) {
uptr->u5 |= (ER1_RMR);
@ -567,13 +567,12 @@ tu_write(int ctlr, int unit, int reg, uint32 data) {
uint32
tu_read(int ctlr, int unit, int reg) {
UNIT *uptr = &tu_unit[(ctlr * 8) + (tu_tcr[ctlr] & 07)];
struct df10 *df10;
struct df10 *df10 = &tu_df10[ctlr];
uint32 temp = 0;
int i;
switch(reg) {
case 000: /* control */
df10 = &tu_df10[ctlr];
temp = uptr->u3 & 076;
if (uptr->flags & UNIT_ATT)
temp |= CS1_DVA;
@ -647,8 +646,7 @@ tu_read(int ctlr, int unit, int reg) {
void tu_error(UNIT * uptr, t_stat r)
{
int ctlr = GET_CNTRL(uptr->flags);
DEVICE *dptr;
dptr = tu_devs[ctlr];
DEVICE *dptr = tu_devs[ctlr];
switch (r) {
case MTSE_OK: /* no error */
@ -958,8 +956,11 @@ t_stat tu_srv(UNIT * uptr)
switch (r) {
case MTSE_OK: /* no error */
break;
case MTSE_BOT: /* beginning of tape */
uptr->u5 |= ER1_NEF;
/* Fall Through */
case MTSE_TMK: /* tape mark */
case MTSE_EOM: /* end of medium */
if (tu_frame[ctlr] != 0)