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SEL32: Correct right halfword nop processing.

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SEL32: Add track/sector replacement support for HSDP.
SEL32: DO some general code cleanup.
This commit is contained in:
AZBevier 2021-01-23 15:42:16 -07:00
parent 4755c20b4e
commit 51d47a7346
11 changed files with 760 additions and 476 deletions
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4
SEL32/README.md
View File

@ -49,7 +49,7 @@ diag.tap bootable level one diagnostic tape w/auto testing. Set
cpu models now run all diagnostics provided on the
diagnostic tape. Running DEXP stand alone causes input
to stop after a few characters are entered. More
itesting is still required.
testing is still required.
CV.CSL - Firmware control diag. Disabled in auto testing.
CV.CP1 - CPU diag part 1 runs OK.
@ -93,5 +93,5 @@ Other MPX verion support:
disk image of a bootable system.
James C. Bevier
06/30/2020
01/23/2021

72
SEL32/sel32_chan.c
View File

@ -224,7 +224,6 @@ int32 RDYQ_Put(uint32 entry)
//ZZwaitrdyq = 8;
//XXwaitrdyq = 5;
// waitrdyq = 2;
// waitrdyq = 1; /* wait at least 1 instruction */
waitrdyq = 1; /* wait at least 1 instruction */
#endif
return SCPE_OK; /* all OK */
@ -510,6 +509,14 @@ int readfull(CHANP *chp, uint32 maddr, uint32 *word)
}
*word = RMW(maddr); /* get 1 word */
sim_debug(DEBUG_XIO, &cpu_dev, "READFULL read %08x from addr %08x\n", *word, maddr);
#if 0
#define DO_DYNAMIC_DEBUG
#ifdef DO_DYNAMIC_DEBUG
if (*word == 0x0a0030a1) {
cpu_dev.dctrl |= DEBUG_INST; /* start instruction trace */
}
#endif
#endif
return 0; /* return OK */
}
@ -614,7 +621,7 @@ loop:
return 1;
}
#ifdef WHATISTHIS
#ifdef DONOTUSETHIS
/* Check if we have status modifier set */
if (chp->chan_status & STATUS_MOD) {
chp->chan_caw += 8; /* move to next IOCD */
@ -645,6 +652,16 @@ loop:
chp->chan_caw = (chp->chan_caw & 0xfffffc) + 8; /* point to next IOCD */
chp->ccw_cmd = (word1 >> 24) & 0xff; /* set command from IOCD wd 1 */
/* Check if we had data chaining in previous iocd */
/* if we did, use previous cmd value */
if (((chp->chan_info & INFO_SIOCD) == 0) && /* see if 1st IOCD in channel prog */
(chp->ccw_flags & FLAG_DC)) { /* last IOCD have DC set? */
sim_debug(DEBUG_CMD, &cpu_dev,
"ec_iocl @%06x DO DC, ccw_flags %04x cmd %02x\n",
chp->chan_caw, chp->ccw_flags, chp->ccw_cmd);
} else
chp->ccw_cmd = (word1 >> 24) & 0xff; /* set new command from IOCD wd 1 */
if (!MEM_ADDR_OK(word1 & MASK24)) { /* see if memory address invalid */
chp->chan_status |= STATUS_PCHK; /* bad, program check */
//** uptr->SNS |= SNS_INAD; /* invalid address status */
@ -699,7 +716,6 @@ loop:
"load_ccw tic cmd bad address chan %02x tic caw %06x IOCD wd 1 %08x\n",
chan, chp->chan_caw, word1);
chp->chan_status |= STATUS_PCHK; /* program check for invalid tic */
// chp->chan_caw = word1; /* get new IOCD address */
chp->chan_caw = word1 & MASK24; /* get new IOCD address */
//** uptr->SNS |= SNS_CMDREJ; /* cmd rejected status */
//** uptr->SNS |= SNS_INAD; /* invalid address status */
@ -712,7 +728,6 @@ loop:
chan, chp->chan_caw, word1);
goto loop; /* restart the IOCD processing */
}
// chp->chan_caw = word1; /* get new IOCD address */
chp->chan_caw = word1 & MASK24; /* get new IOCD address */
chp->chan_status |= STATUS_PCHK; /* program check for invalid tic */
//** uptr->SNS |= SNS_CMDREJ; /* cmd rejected status */
@ -754,7 +769,6 @@ loop:
#ifndef NOT_FOR_EVERYONE
/* DC can only be used with a read/write cmd */
if (chp->ccw_flags & FLAG_DC) {
// if ((chp->ccw_cmd != DSK_RD) && (chp->ccw_cmd != DSK_WD)) {
if ((chp->ccw_cmd != 0x02) && (chp->ccw_cmd != 0x01)) {
chp->chan_status |= STATUS_PCHK; /* program check for invalid DC */
//** uptr->SNS |= SNS_CHER; /* chaining error */
@ -799,8 +813,6 @@ loop:
if (chp->chan_status & (STATUS_ATTN|STATUS_ERROR)) {
chp->chan_status |= STATUS_CEND; /* channel end status */
chp->ccw_flags = 0; /* no flags */
// /* see if chan_end already called */
// if (chp->chan_byte == BUFF_NEXT) {
/* see if chan_end already called */
if (chp->chan_info & INFO_CEND) {
sim_debug(DEBUG_EXP, &cpu_dev,
@ -821,7 +833,7 @@ loop:
/* NOTE this code needed for MPX 1.X to run! */
/* see if command completed */
/* we have good status */
/* TODO Test if chan_end called? */
/* TODO Test if chan_end called? */
if (chp->chan_status & (STATUS_DEND|STATUS_CEND)) {
uint16 chsa = GET_UADDR(uptr->u3); /* get channel & sub address */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* show I/O complete */
@ -898,8 +910,7 @@ int test_write_byte_end(uint16 chsa)
return 1; /* return done */
if (chp->ccw_count == 0) {
if ((chp->ccw_flags & FLAG_DC) == 0) { /* see if we have data chaining */
//1003 chp->chan_status |= STATUS_CEND; /* no, end of data */
/*122320*/ chp->chan_byte = BUFF_CHNEND; /* thats all the data we want */
chp->chan_byte = BUFF_CHNEND; /* thats all the data we want */
//sim_debug(DEBUG_EXP, &cpu_dev,
//"test_write_byte BUFF_CHNEND chp %p chan_byte %04x\n", chp, chp->chan_byte);
return 1; /* return done */
@ -1165,7 +1176,6 @@ void chan_end(uint16 chsa, uint16 flags) {
store_csw(chp); /* store the status */
/* change chan_byte to BUFF_POST */
chp->chan_byte = BUFF_POST; /* show done with data */
// chp->chan_status = 0; /* no status anymore */
chp->ccw_cmd = 0; /* no command anymore */
if (chp->chan_status & STATUS_ERROR) { /* check channel error status */
@ -1263,7 +1273,6 @@ int16 post_csw(CHANP *chp, uint32 rstat)
chsa, FIFO_Num(chsa), incha, chan_icb, sw1, sw2);
return 1; /* show we posted status */
}
// 717 added
sim_debug(DEBUG_EXP, &cpu_dev,
"post_csw %04x chp %p READ FIFO #%1x inch %06x No Status chan_byte %02x\n",
chsa, chp, FIFO_Num(chsa), incha, chp->chan_byte);
@ -1289,6 +1298,8 @@ void store_csw(CHANP *chp)
sim_debug(DEBUG_XIO, &cpu_dev,
"store_csw FIFO #%1x write chsa %04x sw1 %08x sw2 %08x incha %08x cmd %02x\n",
FIFO_Num(chsa), chsa, stwd1, stwd2, chp->chan_inch_addr, chp->ccw_cmd);
/* added 011321 */
INTS[chp->chan_int] |= INTS_REQ; /* request an interrupt for channel */
irq_pend = 1; /* wakeup controller */
}
@ -1386,7 +1397,10 @@ t_stat startxio(uint16 lchsa, uint32 *status) {
uint16 lchan = get_chan(lchsa); /* get the logical channel number */
uint16 chsa;
uint32 tempa, inta, spadent, chan, incha;
uint32 word1, word2, cmd, itva;
uint32 word1, word2, cmd;
#ifdef DEBUG_DISK
uint32 itva;
#endif
DEVICE *dptr;
sim_debug(DEBUG_XIO, &cpu_dev, "startxio entry logical chsa %04x\n", lchsa);
@ -1399,13 +1413,9 @@ t_stat startxio(uint16 lchsa, uint32 *status) {
sim_debug(DEBUG_XIO, &cpu_dev,
"startxio entry inta %02x lchan %04x spadent %08x rchsa %04x\n",
inta, lchan, spadent, chsa);
dibp = dib_unit[chsa & 0x7f00]; /* get the device information pointer */
// uptr = find_unit_ptr(chsa); /* find pointer to unit on channel */
/* FIXME */
/* chp will be NULL for odd disk address */
// chp = find_chanp_ptr(chsa); /* find the chanp pointer */
uptr = find_unit_ptr(chsa&0x7f00); /* get unit 0 unit pointer */
dibp = dib_unit[chsa & 0x7f00]; /* get the device information pointer */
uptr = find_unit_ptr(chsa & 0x7f00); /* get unit 0 unit pointer */
if (uptr != NULL) {
dptr = get_dev(uptr); /* get device address */
if ((dptr != NULL) &&
@ -1413,8 +1423,8 @@ t_stat startxio(uint16 lchsa, uint32 *status) {
chsa = chsa & 0x7ffe; /* clear the odd subaddress */
}
}
#ifndef DEBUG_DISK
// chan_icb = find_int_icb(lchsa); /* Interrupt level context block address */
chan_icb = find_int_icb(lchsa); /* Interrupt level context block address */
#ifdef DEBUG_DISK
itva = SPAD[0xf1] + (inta<<2); /* int vector address */
chan_icb = RMW(itva); /* Interrupt context block addr */
iocla = RMW(chan_icb+16); /* iocla is in wd 4 of ICB */
@ -1456,8 +1466,8 @@ missing:
return SCPE_OK; /* not found, CC3 */
}
#ifdef FOR_DEBUG
// inta = find_int_lev(chsa); /* Interrupt Level for channel */
#ifndef FOR_DEBUG
if ((INTS[inta]&INTS_ACT) || (SPAD[inta+0x80]&SINT_ACT)) { /* look for level active */
/* just output a warning */
sim_debug(DEBUG_XIO, &cpu_dev,
@ -1478,7 +1488,6 @@ missing:
/* ethernet controller wants an interrupt for busy status */
if ((dptr != NULL) &&
(DEV_TYPE(dptr) == DEV_ETHER)) { /* see if this is ethernet */
// if (DEV_TYPE(dptr) == DEV_ETHER) {
*status = CC1BIT; /* CCs = 1, SIO accepted & queued, no echo status */
/* handle an Ethernet controller busy by sending interrupt/status */
chp->chan_status = STATUS_BUSY|STATUS_CEND|STATUS_DEND; /* set busy status */
@ -1685,7 +1694,6 @@ t_stat testxio(uint16 lchsa, uint32 *status) { /* test XIO */
"TIO rchsa %04x LOOK FIFO #%1x irq %02x inch %06x chp %p icba %06x chan_byte %02x\n",
rchsa, FIFO_Num(rchsa), inta, chp->chan_inch_addr, chp, chan_icb, chp->chan_byte);
if (post_csw(chp, 0)) {
//120120/*112120*/ chp->chan_byte = BUFF_DONE; /* show done & not busy */
sim_debug(DEBUG_IRQ, &cpu_dev,
"TIO rchsa %04x POST FIFO #%1x irq %02x inch %06x chan_icba+20 %08x chan_byte %02x\n",
rchsa, FIFO_Num(rchsa), inta, chp->chan_inch_addr, RMW(chan_icb+20), chp->chan_byte);
@ -1805,7 +1813,6 @@ t_stat stopxio(uint16 lchsa, uint32 *status) { /* stop XIO */
chp->ccw_count = 0; /* zero the count */
/* post status for UTX */
if (post_csw(chp, ((STATUS_PCI) << 16))) {
//120120/*112120*/ chp->chan_byte = BUFF_DONE; /* show done & not busy */
INTS[inta] &= ~INTS_REQ; /* clear any level request */
*status = CC2BIT; /* status stored */
sim_debug(DEBUG_CMD, &cpu_dev,
@ -1872,9 +1879,7 @@ t_stat rschnlxio(uint16 lchsa, uint32 *status) { /* reset channel XIO */
sim_debug(DEBUG_XIO, &cpu_dev, "rschnlxio entry lchan %04x rchan %04x\n", lchan, rchan);
/* get the device entry for the logical channel in SPAD */
// dibp = dib_chan[get_chan(rchsa)]; /* get the channel device information pointer */
dibp = dib_unit[rchsa]; /* get the channel device information pointer */
// chp = find_chanp_ptr(rchan); /* find the channel chanp pointer */
chp = find_chanp_ptr(rchsa); /* find the channel chanp pointer */
if (dibp == 0 || chp == 0) { /* if no dib or channel ptr, CC3 return */
@ -2011,7 +2016,6 @@ t_stat haltxio(uint16 lchsa, uint32 *status) { /* halt XIO */
chp->ccw_count = 0; /* zero the count */
/* post status for UTX */
if (post_csw(chp, ((STATUS_PCI) << 16))) {
//120120/*112120*/ chp->chan_byte = BUFF_DONE; /* show done & not busy */
INTS[inta] &= ~INTS_REQ; /* clear any level request */
*status = CC2BIT; /* status stored */
sim_debug(DEBUG_CMD, &cpu_dev,
@ -2070,7 +2074,6 @@ t_stat haltxio(uint16 lchsa, uint32 *status) { /* halt XIO */
#ifndef JUNK
chp->chan_byte = BUFF_DONE; /* we are done */
sim_debug(DEBUG_EXP, &cpu_dev, "haltxio BUFF_DONE chp %p chan_byte %04x\n", chp, chp->chan_byte);
//1204 chp->chan_status = (STATUS_DEND|STATUS_CEND);
/*1204*/chp->chan_status = (STATUS_DEND|STATUS_CEND|STATUS_EXPT);
store_csw(chp); /* store the status */
/* change chan_byte to BUFF_POST */
@ -2102,7 +2105,6 @@ sim_debug(DEBUG_EXP, &cpu_dev, "haltxio BUFF_DONE chp %p chan_byte %04x\n", chp,
chp->ccw_count = 0; /* zero the count */
/* remove SLI, PPCI and Unit check status bits */
if (post_csw(chp, ((STATUS_PCI) << 16))) {
//120120/*112120*/ chp->chan_byte = BUFF_DONE; /* show done & not busy */
INTS[inta] &= ~INTS_REQ; /* clear any level request */
*status = CC2BIT; /* status stored from SIO, so CC2 */
sim_debug(DEBUG_CMD, &cpu_dev,
@ -2320,6 +2322,13 @@ t_stat chan_boot(uint16 chsa, DEVICE *dptr) {
chp->ccw_flags = 0; /* Command chain and supress incorrect length */
chp->chan_info = INFO_SIOCD; /* show first IOCD in channel prog */
chp->ccw_cmd = 0; /* read command */
/* moved here to not destry loc 0-0x14 on reset/go cmds */
M[0] = 0x02000000; /* 0x00 IOCD 1 read into address 0 */
M[1] = 0x60000078; /* 0x04 IOCD 1 CMD Chain, Suppress incor length, 120 bytes */
M[2] = 0x53000000; /* 0x08 IOCD 2 BKSR or RZR to re-read boot code */
M[3] = 0x60000001; /* 0x0C IOCD 2 CMD chain,Supress incor length, 1 byte */
M[4] = 0x02000000; /* 0x10 IOCD 3 Read into address 0 */
M[5] = 0x000006EC; /* 0x14 IOCD 3 Read 0x6EC bytes */
loading = chsa; /* show we are loading from the boot device */
sim_debug(DEBUG_CMD, &cpu_dev, "Channel Boot calling load_ccw chan %04x status %08x\n",
@ -2512,7 +2521,7 @@ uint32 scan_chan(uint32 *ilev) {
#else
if (CPUSTATUS & BIT24) { /* interrupts blocked? */
#endif
if (waitqcnt) /* interrupts blocked? */
if (waitqcnt) /* doing wait delay? */
sim_debug(DEBUG_DETAIL, &cpu_dev,
// sim_debug(DEBUG_IRQ, &cpu_dev,
"scan_chan waitqcnt %02x\n", waitqcnt);
@ -2587,7 +2596,6 @@ uint32 scan_chan(uint32 *ilev) {
"scan_chan %04x LOOK FIFO #%1x irq %02x inch %06x chp %p icba %06x chan_byte %02x\n",
chsa, FIFO_Num(chan), i, chp->chan_inch_addr, chp, chan_icba, chp->chan_byte);
if (post_csw(chp, 0)) {
//120120/*112120*/ chp->chan_byte = BUFF_DONE; /* show done & not busy */
sim_debug(DEBUG_IRQ, &cpu_dev,
"scan_chanx %04x POST FIFO #%1x irq %02x inch %06x chan_icba+20 %08x chan_byte %02x\n",
chan, FIFO_Num(chan), i, chp->chan_inch_addr, RMW(chan_icba+20), chp->chan_byte);

4
SEL32/sel32_com.c
View File

@ -376,7 +376,9 @@ void com_ini(UNIT *uptr, t_bool f)
DEVICE *dptr = get_dev(uptr);
sim_debug(DEBUG_CMD, dptr, "COM init device %s controller 0x7e00\n", dptr->name);
sim_activate(uptr, 1000); /* time increment */
//01sim_activate(uptr, 1000); /* time increment */
sim_cancel(uptr); /* stop input poll */
sim_activate(uptr, 1000); /* start input poll */
}
/* called from sel32_chan to start an I/O operation */

17
SEL32/sel32_con.c
View File

@ -54,13 +54,13 @@
/* Status held in u3 */
/* controller/unit address in upper 16 bits */
#define CON_INPUT 0x0100 /* Input ready for unit */
#define CON_CR 0x0200 /* Output at beginning of line */
#define CON_REQ 0x0400 /* Request key pressed */
#define CON_EKO 0x0800 /* Echo input character */
#define CON_OUTPUT 0x1000 /* Output ready for unit */
#define CON_READ 0x2000 /* Read mode selected */
#define CON_ATAT 0x4000 /* working on @@A input */
#define CON_READ 0x2000 /* Read mode selected */
#define CON_OUTPUT 0x1000 /* Output ready for unit */
#define CON_EKO 0x0800 /* Echo input character */
#define CON_REQ 0x0400 /* Request key pressed */
#define CON_CR 0x0200 /* Output at beginning of line */
#define CON_INPUT 0x0100 /* Input ready for unit */
/* Input buffer pointer held in u4 */
@ -156,7 +156,10 @@ void con_ini(UNIT *uptr, t_bool f) {
con_data[unit].incnt = 0; /* no input data */
uptr->CMD &= LMASK; /* leave only chsa */
uptr->SNS = SNS_RDY|SNS_ONLN; /* status is online & ready */
sim_activate(uptr, 1000); /* time increment */
if (unit == 0) {
sim_cancel(uptr); /* stop input poll */
sim_activate(uptr, 1000); /* start input poll */
}
}
/* start a console operation */

172
SEL32/sel32_cpu.c
View File

@ -1656,11 +1656,13 @@ t_stat Mem_read(uint32 addr, uint32 *data)
}
/* everybody else has read access */
}
sim_debug(DEBUG_DETAIL, &cpu_dev, "Mem_read addr %06x realaddr %06x data %08x prot %02x\n",
sim_debug(DEBUG_DETAIL, &cpu_dev,
"Mem_read addr %06x realaddr %06x data %08x prot %02x\n",
addr, realaddr, *data, prot);
} else {
/* RealAddr returned an error */
sim_debug(DEBUG_EXP, &cpu_dev, "Mem_read error addr %06x realaddr %06x data %08x prot %02x status %04x\n",
sim_debug(DEBUG_EXP, &cpu_dev,
"Mem_read error addr %06x realaddr %06x data %08x prot %02x status %04x\n",
addr, realaddr, *data, prot, status);
if (status == NPMEM) { /* operand nonpresent memory error */
if ((CPU_MODEL == MODEL_97) || (CPU_MODEL == MODEL_V9)) {
@ -1891,11 +1893,19 @@ wait_loop:
sim_interval--; /* count down */
#ifndef NOT_NEEDED_0120
if (drop_nop) { /* need to drop a nop? */
PSD1 = (PSD1 + 2) | (((PSD1 & 2) >> 1) & 1); /* skip this instruction */
PSD1 &= ~BIT31; /* clear bit 31, no lr */
// int sav = PSD1;
// PSD1 = (PSD1 + 2) | (((PSD1 & 2) >> 1) & 1); /* skip this instruction */
// PSD1 &= ~BIT31; /* clear bit 31, no lr */
drop_nop = 0; /* we dropped the nop */
sim_debug(DEBUG_CMD, &cpu_dev,
// "CPU Drop NOP BF PSD1 %08x AF PSD1 %08x\n", sav, PSD1);
"CPU Drop NOP PSD1 %08x\n", PSD1);
}
#else
drop_nop = 0; /* we dropped the nop */
#endif
if (skipinstr) { /* need to skip interrupt test? */
skipinstr = 0; /* skip only once */
@ -1981,7 +1991,8 @@ wait_loop:
M[int_icb>>2] = PSD1&0xfffffffe;/* store PSD 1 */
M[(int_icb>>2)+1] = PSD2; /* store PSD 2 */
PSD1 = M[(int_icb>>2)+2]; /* get new PSD 1 */
PSD2 = (M[(int_icb>>2)+3] & ~0x3ff8) | bc; /* get new PSD 2 w/old cpix */
//0120 PSD2 = (M[(int_icb>>2)+3] & ~0x3ff8) | bc; /* get new PSD 2 w/old cpix */
PSD2 = (M[(int_icb>>2)+3] & ~0x3fff) | bc; /* get new PSD 2 w/old cpix */
/* I/O status DW address will be in WD 6 */
/* set new map mode and interrupt blocking state in CPUSTATUS */
@ -2065,7 +2076,8 @@ wait_loop:
goto skipi; /* skip int test */
}
}
#ifndef NEEDS_FIXING
/* process IOCL entries that are waiting */
if (RDYQ_Num()) {
uint32 chsa; /* channel/sub adddress */
CHANP *chp; /* get channel prog pointer */
@ -2096,30 +2108,6 @@ wait_loop:
}
}
}
#else
if (RDYQ_Num()) {
uint32 chsa; /* channel/sub adddress */
int32 stat;
/* we have entries, continue channel program */
if (RDYQ_Get(&chsa) == SCPE_OK) { /* get chsa for program */
CHANP *chp = find_chanp_ptr(chsa); /* get channel prog pointer */
sim_debug(DEBUG_XIO, &cpu_dev,
"scan_chan CPU RDYQ entry for chsa %04x starting byte %02x\n",
chsa, chp->chan_byte);
stat = cont_chan(chsa); /* resume the channel program */
if (stat == SCPE_OK)
sim_debug(DEBUG_XIO, &cpu_dev,
"scan_chan CPU RDYQ entry for chsa %04x processed byte %04x\n",
chsa, chp->chan_byte);
else
sim_debug(DEBUG_XIO, &cpu_dev,
"scan_chan CPU RDYQ entry for chsa %04x processed w/error byte %04x\n",
chsa, chp->chan_byte);
}
// goto wait_loop; /*1119*/ /* continue waiting */
}
#endif
/* see if in wait instruction */
if (wait4int) { /* keep waiting */
@ -2194,6 +2182,7 @@ skipi:
"2Rt HW instruction skipinstr %1x is set PSD1 %08x PSD2 %08x CPUSTATUS %08x\n",
skipinstr, PSD1, PSD2, CPUSTATUS);
goto skipi; /* go read next instruction */
/////0122 goto wait_loop; /* continue waiting */
}
if (skipinstr)
sim_debug(DEBUG_IRQ, &cpu_dev,
@ -2214,6 +2203,8 @@ skipi:
if ((IR & 0xffff) == 0x0002) { /* see if rt hw is a nop */
/* treat this as a fw instruction */
drop_nop = 1; /* we need to skip nop next time */
sim_debug(DEBUG_DETAIL, &cpu_dev,
"CPU setting Drop NOP PSD1 %08x IR %08x\n", PSD1, IR);
}
}
}
@ -2227,8 +2218,8 @@ exec:
/* Split instruction into pieces */
PC = PSD1 & 0xfffffe; /* get 24 bit addr from PSD1 */
sim_debug(DEBUG_DETAIL, &cpu_dev, "-----Instr @ PC %08x PSD1 %08x PSD2 %08x IR %08x\n",
PC, PSD1, PSD2, IR);
sim_debug(DEBUG_DETAIL, &cpu_dev, "-----Instr @ PC %08x PSD1 %08x PSD2 %08x IR %08x drop_nop %x\n",
PC, PSD1, PSD2, IR, drop_nop);
/* Update history for this instruction */
if (hst_lnt) {
@ -2582,7 +2573,6 @@ exec:
}
sim_debug(DEBUG_EXP, &cpu_dev, "Starting HALT instruction\n");
// if (cpu_dev.dctrl & DEBUG_EXP) {
sim_debug(DEBUG_EXP, &cpu_dev, "\n[][][][][][][][][][] HALT [][][][][][][][][][]\n");
sim_debug(DEBUG_EXP, &cpu_dev, "PSD1 %.8x PSD2 %.8x TRAPME %.4x CPUSTATUS %08x\n",
PSD1, PSD2, TRAPME, CPUSTATUS);
@ -2590,7 +2580,7 @@ exec:
sim_debug(DEBUG_EXP, &cpu_dev, "GPR[%d] %.8x GPR[%d] %.8x\n", ix, GPR[ix], ix+1, GPR[ix+1]);
}
sim_debug(DEBUG_EXP, &cpu_dev, "[][][][][][][][][][] HALT [][][][][][][][][][]\n");
// }
fprintf(stdout, "\r\n[][][][][][][][][][] HALT [][][][][][][][][][]\r\n");
fprintf(stdout, "PSD1 %.8x PSD2 %.8x TRAPME %.4x\r\n", PSD1, PSD2, TRAPME);
for (ix=0; ix<8; ix+=2) {
@ -2631,7 +2621,7 @@ exec:
wait4int = 1; /* show we are waiting for interrupt */
/* tell simh we will be waiting */
sim_idle(TMR_RTC, 0); /* wait for next pending device event */
/*719*/ irq_pend = 1; /* start scanning interrupts again */
irq_pend = 1; /* start scanning interrupts again */
i_flags |= BT; /* keep PC from being incremented while waiting */
break;
case 0x2: /* NOP */
@ -2954,21 +2944,8 @@ exec:
if ((GPR[reg] & 0x80000000) && (CPU_MODEL == MODEL_V9)) {
/* if bit 0 of reg set, return Cache/Shadow Configuration Word */
CMSMC = 0xffff0000; /* no CPU/IPU Cache/Shadow unit present */
//@42 CMSMC = 0x00ff0000; /* no IPU Cache/Shadow unit present */
//@42 CMSMC = 0x00000000; /* no IPU Cache/Shadow unit present */
/*@42*/ CMSMC |= 0x00000000; /* CPU Cache/Shadow unit present */
//@42 CMSMC |= 0x0000c000; /* MACC not present in CP1/CP2 */
// CMSMC |= 0x00000000; /* MACC present in CP1 */
//@42 CMSMC |= 0x00008000; /* MACC not present in CP1 */
// CMSMC |= 0x00000000; /* MACC present in CP2 */
//@42 CMSMC |= 0x00004000; /* MACC not present in CP1/CP2 */
//@42 CMSMC |= 0x00003000; /* CP1/CP2 not present */
// CMSMC |= 0x00000000; /* CP1 present */
//@42 CMSMC |= 0x00002000; /* CP1 not present */
// CMSMC |= 0x00000000; /* CP2 present */
//@42 CMSMC |= 0x00001000; /* CP2 not present */
CMSMC |= 0x00000800; /* bit 20, IPU not present */
//@42 CMSMC |= 0x00000400; /* Shared Memory not configured */
CMSMC |= 0x00000200; /* bit 22, Access Protection ECO present */
CMSMC |= 0x0000001f; /* CPU Firmware Version 1/Rev level 0 */
dest = CMSMC; /* return starus */
@ -3639,7 +3616,6 @@ tbr: /* handle basemode TBR too *
CPUSTATUS |= BIT22; /* HS Floating is set to off */
/* make sure WCS is off and prom mode set to 0 (on) */
CPUSTATUS &= ~(BIT20|BIT21); /* make zero */
// sim_debug(DEBUG_EXP, &cpu_dev,
sim_debug(DEBUG_CMD, &cpu_dev,
"SETCPU orig %08x user bits %08x New CPUSTATUS %08x\n",
temp2, temp, CPUSTATUS);
@ -3778,7 +3754,8 @@ skipit:
M[t>>2] = PSD1 & 0xfffffffe; /* store PSD 1 + 1HW to point to next instruction */
M[(t>>2)+1] = PSD2; /* store PSD 2 */
PSD1 = M[(t>>2)+2]; /* get new PSD 1 */
PSD2 = (M[(t>>2)+3] & ~0x3ff8) | bc; /* get new PSD 2 w/old cpix */
//0120 PSD2 = (M[(t>>2)+3] & ~0x3ff8) | bc; /* get new PSD 2 w/old cpix */
PSD2 = (M[(t>>2)+3] & ~0x3fff) | bc; /* get new PSD 2 w/old cpix */
M[(t>>2)+4] = opr & 0x03FF; /* store calm number in bits 6-15 */
/* set the mode bits and CCs from the new PSD */
@ -5372,6 +5349,7 @@ doovr2:
case 0x6: /* SVC none - none */ /* Supervisor Call Trap */
int32c = CPUSTATUS; /* keep for retain blocking state */
addr = SPAD[0xf0]; /* get trap table memory address from SPAD (def 80) */
int32a = addr;
if (addr == 0 || addr == 0xffffffff) { /* see if secondary vector table set up */
TRAPME = ADDRSPEC_TRAP; /* Not setup, error */
goto newpsd; /* program error */
@ -5388,16 +5366,30 @@ doovr2:
TRAPME = ADDRSPEC_TRAP; /* Not setup, error */
goto newpsd; /* program error */
}
#if 0
#define DO_DYNAMIC_DEBUG
#ifdef DO_DYNAMIC_DEBUG
if ((IR&0xfff) == 0x37) {
cpu_dev.dctrl |= (DEBUG_INST|DEBUG_DETAIL); /* start instruction trace */
}
#endif
#endif
#ifdef NOT_NOW
sim_debug(DEBUG_IRQ, &cpu_dev,
"SVC IR %08x #%02x call #%03x TTA %04x SVCTA %06x 2ndTTA %06x\n",
IR, temp2>>2, IR&0xFFF, int32a, temp, t);
#endif
bc = PSD2 & 0x3ff8; /* get copy of cpix */
M[t>>2] = (PSD1+4) & 0xfffffffe; /* store PSD 1 + 1W to point to next instruction */
M[(t>>2)+1] = PSD2; /* store PSD 2 */
PSD1 = M[(t>>2)+2]; /* get new PSD 1 */
PSD2 = (M[(t>>2)+3] & ~0x3ff8) | bc; /* get new PSD 2 w/old cpix */
//0120 PSD2 = (M[(t>>2)+3] & ~0x3ff8) | bc; /* get new PSD 2 w/old cpix */
PSD2 = (M[(t>>2)+3] & ~0x3fff) | bc; /* get new PSD 2 w/old cpix */
M[(t>>2)+4] = IR&0xFFF; /* store call number */
#ifdef NOT_NOW
sim_debug(DEBUG_IRQ, &cpu_dev,
"SVC #%02x call #%03x PSD1 %08x PSD2 %08x CPUSTATUS %08x\n",
temp2, IR&0xFFF, PSD1, PSD2, CPUSTATUS);
temp2>>2, IR&0xFFF, PSD1, PSD2, CPUSTATUS);
#endif
/* set the mode bits and CCs from the new PSD */
CC = PSD1 & 0x78000000; /* extract bits 1-4 from PSD1 */
@ -6009,7 +6001,8 @@ temp2, IR&0xFFF, PSD1, PSD2, CPUSTATUS);
TRAPSTATUS |= BIT18; /* set bit 18 of trap status */
goto newpsd; /* memory read error or map fault */
}
PSD2 = temp2; /* PSD2 access good, so save it */
//0120 PSD2 = temp2; /* PSD2 access good, so save it */
PSD2 = temp2 & 0xfffffff8; /* PSD2 access good, clean & ave it */
} else {
if ((TRAPME = Mem_read(addr+4, &temp2))) { /* get PSD2 from memory */
if ((CPU_MODEL == MODEL_97) || (CPU_MODEL == MODEL_V9)) {
@ -6020,8 +6013,11 @@ temp2, IR&0xFFF, PSD1, PSD2, CPUSTATUS);
goto newpsd; /* memory read error or map fault */
}
/* lpsd can not change cpix, so keep it */
PSD2 = ((PSD2 & 0x3fff) | (temp2 & 0xffffc000)); /* use current cpix */
//0120 PSD2 = ((PSD2 & 0x3fff) | (temp2 & 0xffffc000)); /* use current cpix */
PSD2 = ((PSD2 & 0x3ff8) | (temp2 & 0xffffc000)); /* use current cpix */
}
sim_debug(DEBUG_IRQ, &cpu_dev,
"LPSD(CM) load New PSD1 %08x PSD2 %08x\n", PSD1, PSD2);
PSD1 = temp; /* PSD1 good, so set it */
/* set the mode bits and CCs from the new PSD */
@ -6061,14 +6057,14 @@ temp2, IR&0xFFF, PSD1, PSD2, CPUSTATUS);
} else {
#ifdef NOTRIGHT
/* handle retain blocking state */
PSD2 &= ~RETMBIT; /* turn off retain bit in PSD2 */
PSD2 &= ~RETMBIT; /* turn off retain bit in PSD2 */
#endif
/* set new blocking state in PSD2 */
PSD2 &= ~(SETBBIT|RETBBIT); /* clear bit 48 & 49 to be unblocked */
MODES &= ~(BLKMODE|RETMODE);/* reset blocked & retain mode bits */
if (bc & BIT24) { /* see if old mode is blocked */
PSD2 |= SETBBIT; /* set to blocked state */
MODES |= BLKMODE; /* set blocked mode */
PSD2 &= ~(SETBBIT|RETBBIT); /* clear bit 48 & 49 to be unblocked */
MODES &= ~(BLKMODE|RETMODE); /* reset blocked & retain mode bits */
if (bc & BIT24) { /* see if old mode is blocked */
PSD2 |= SETBBIT; /* set to blocked state */
MODES |= BLKMODE; /* set blocked mode */
}
}
@ -6077,13 +6073,16 @@ temp2, IR&0xFFF, PSD1, PSD2, CPUSTATUS);
if (PSD2 & MAPBIT) {
/* set mapped mode in cpu status */
CPUSTATUS |= BIT8; /* set bit 8 of cpu status */
sim_debug(DEBUG_DETAIL, &cpu_dev,
#ifdef NOT_NOW
// sim_debug(DEBUG_DETAIL, &cpu_dev,
sim_debug(DEBUG_IRQ, &cpu_dev,
"B4 LPSDCM temp %06x TPSD %08x %08x PSD %08x %08x\n",
temp, TPSD[0], TPSD[1], PSD1, PSD2);
sim_debug(DEBUG_DETAIL, &cpu_dev,
// sim_debug(DEBUG_DETAIL, &cpu_dev,
sim_debug(DEBUG_IRQ, &cpu_dev,
"B4 LPSDCM BPIX %04x CPIX %04x CPIXPL %04x\n",
BPIX, CPIX, CPIXPL);
#endif
/* this mod fixes MPX 1.X 1st swapr load */
/* any O/S or user maps yet? */
if (((CPIX != 0) && (CPIXPL == 0)) && (PSD2 & RETMBIT)) {
@ -6114,6 +6113,7 @@ TPSD[0], TPSD[1], PSD1, PSD2, TRAPME);
if ((PSD2 & RETMBIT) == 0) { /* don't load maps if retain bit set */
/* we need to load the new maps */
TRAPME = load_maps(PSD, 0); /* load maps for new PSD */
#ifdef NOT_NOW
// sim_debug(DEBUG_DETAIL, &cpu_dev,
sim_debug(DEBUG_IRQ, &cpu_dev,
"AF LPSDCM TPSD %08x %08x PSD %08x %08x TRAPME %02x\n",
@ -6131,6 +6131,7 @@ TPSD[0], TPSD[1], PSD1, PSD2, TRAPME);
"AF LPSDCM US MAPC[%x-%x] %08x %08x %08x %08x %08x %08x\n",
BPIX, BPIX+5, MAPC[BPIX], MAPC[BPIX+1], MAPC[BPIX+2],
MAPC[BPIX+3], MAPC[BPIX+4], MAPC[BPIX+5]);
#endif
}
PSD2 &= ~RETMBIT; /* turn off retain bit in PSD2 */
SPAD[0xf5] = PSD2; /* save the current PSD2 */
@ -6450,6 +6451,9 @@ TPSD[0], TPSD[1], PSD1, PSD2, TRAPME);
sim_debug(DEBUG_XIO, &cpu_dev,
"$$ XIO SYSTEMCHK lchan %04x sa %04x spad %08x BLK %1x INTS[%02x] %08x\n",
lchan, suba, t, CPUSTATUS&0x80?1:0, ix, INTS[ix]);
sim_debug(DEBUG_XIO, &cpu_dev,
"$$ XIO SYSTEMCHK2 IR %08x temp2 %04x lchsa %04x opr %02x GPR[%02x] %08x\n",
IR, temp2, lchsa, (opr>>3)&0xf, reg, GPR[reg]);
TRAPME = SYSTEMCHK_TRAP; /* trap condition if F class */
TRAPSTATUS |= BIT0; /* class F error bit */
TRAPSTATUS &= ~BIT1; /* I/O processing error */
@ -6536,11 +6540,9 @@ mcheck:
break;
case 0x02: /* Start I/O SIO */
// chsa = temp2 & 0x7fff; /* logical address */
sim_debug(DEBUG_XIO, &cpu_dev,
"SIO b4 call PSD1 %08x rchsa %04x lchsa %04x BLK %1x\n",
PSD1, rchsa, lchsa, CPUSTATUS&0x80?1:0);
// PSD1, lchan, lchsa, CPUSTATUS&0x80?1:0);
if ((TRAPME = startxio(lchsa, &rstatus)))
goto newpsd; /* error returned, trap cpu */
PSD1 = ((PSD1 & 0x87fffffe) | (rstatus & 0x78000000)); /* insert status */
@ -6550,7 +6552,6 @@ mcheck:
break;
case 0x03: /* Test I/O TIO */
// lchsa = (lchan << 8) | suba; /* logical address */
if ((TRAPME = testxio(lchsa, &rstatus))) {
sim_debug(DEBUG_TRAP, &cpu_dev,
"TIO ret PSD1 %x rchsa %x lchsa %x status %x BLK %1x\n",
@ -6821,11 +6822,17 @@ mcheck:
PSD1 = (PSD1 + 4) | (((PSD1 & 2) >> 1) & 1);
EXM_EXR = 0; /* reset PC increment for EXR */
} else
if (i_flags & HLF) {
PSD1 = (PSD1 + 2) | (((PSD1 & 2) >> 1) & 1);
if (i_flags & HLF) { /* if nop in rt hw, bump pc a word */
if ((drop_nop) && ((CPU_MODEL == MODEL_67) || (CPU_MODEL == MODEL_V6)))
{
PSD1 = (PSD1 + 4) | (((PSD1 & 2) >> 1) & 1);
} else {
PSD1 = (PSD1 + 2) | (((PSD1 & 2) >> 1) & 1);
}
} else {
PSD1 = (PSD1 + 4) | (((PSD1 & 2) >> 1) & 1);
}
drop_nop = 0; /* no NOP to drop */
} else {
EXM_EXR = 0; /* reset PC increment for EXR */
drop_nop = 0; /* no NOP to drop */
@ -6928,7 +6935,7 @@ newpsd:
/* drop through */
default:
sim_debug(DEBUG_TRAP, &cpu_dev,
"##TRAPME %04x LOAD MAPS PSD1 %08x PSD2 %08x CPUSTATUS %08x drop_nop %1x i_flags %04x\n",
"##TRAPME %02x LOAD MAPS PSD1 %08x PSD2 %08x CPUSTATUS %08x drop_nop %1x i_flags %04x\n",
TRAPME, PSD1, PSD2, CPUSTATUS, drop_nop, i_flags);
/* adjust PSD1 to next instruction */
/* Update instruction pointer to next instruction */
@ -6939,12 +6946,12 @@ newpsd:
EXM_EXR = 0; /* reset PC increment for EXR */
} else
if (i_flags & HLF) { /* if nop in rt hw, bump pc a word */
if ((drop_nop) && ((CPU_MODEL == MODEL_67) || (CPU_MODEL == MODEL_V6)))
{
if ((drop_nop) && ((CPU_MODEL == MODEL_67) || (CPU_MODEL == MODEL_V6))) {
PSD1 = (PSD1 + 4) | (((PSD1 & 2) >> 1) & 1);
drop_nop = 0;
} else
} else {
PSD1 = (PSD1 + 2) | (((PSD1 & 2) >> 1) & 1);
}
drop_nop = 0;
} else {
PSD1 = (PSD1 + 4) | (((PSD1 & 2) >> 1) & 1);
//DIAG fix for test 34/10 in MMM diag, reset bit 31
@ -6970,14 +6977,14 @@ newpsd:
PSD1 &= ~BIT31; /* force off last right */
/* pfault will have 11 bit page number and bit 0 set if op fetch */
sim_debug(DEBUG_TRAP, &cpu_dev,
"##PAGEFAULT TRAPS %04x page# %04x LOAD MAPS PSD1 %08x PSD2 %08x CPUSTATUS %08x\n",
"##PAGEFAULT TRAPS %02x page# %04x LOAD MAPS PSD1 %08x PSD2 %08x CPUSTATUS %08x\n",
TRAPME, pfault, PSD1, PSD2, CPUSTATUS);
}
sim_debug(DEBUG_TRAP, &cpu_dev,
"At TRAPME %04x PSD1 %08x PSD2 %08x CPUSTATUS %08x drop_nop %02x\n",
"At TRAPME %02x PSD1 %08x PSD2 %08x CPUSTATUS %08x drop_nop %02x\n",
TRAPME, PSD1, PSD2, CPUSTATUS, drop_nop);
sim_debug(DEBUG_TRAP, &cpu_dev,
"At TRAP %04x IR %08x PSD1 %08x PSD2 %08x CPUSTATUS %08x ovr %01x drop_nop %01x\n",
"At TRAP %02x IR %08x PSD1 %08x PSD2 %08x CPUSTATUS %08x ovr %01x drop_nop %01x\n",
TRAPME, IR, PSD1, PSD2, CPUSTATUS, ovr, drop_nop);
tta = tta + (TRAPME - 0x80); /* tta has mem addr of trap vector */
@ -7020,14 +7027,14 @@ newpsd:
uint32 oldstatus = CPUSTATUS; /* keep for retain blocking state */
/* valid vector, so store the PSD, fetch new PSD */
bc = PSD2 & 0x3ff8; /* get copy of cpix */
if ((TRAPME) && ((CPU_MODEL <= MODEL_27) ))
/* Privlege Mode Halt Trap on 27 has bit 31 reset */
M[tvl>>2] = PSD1 & 0xfffffffe; /* store PSD 1 */
else
if ((TRAPME) && ((CPU_MODEL <= MODEL_27))) {
/* Traps on 27 have bit 31 reset */
M[tvl>>2] = PSD1 & 0xfffffffe; /* store PSD 1 */
} else
M[tvl>>2] = PSD1 & 0xffffffff; /* store PSD 1 */
M[(tvl>>2)+1] = PSD2; /* store PSD 2 */
PSD1 = M[(tvl>>2)+2]; /* get new PSD 1 */
PSD2 = (M[(tvl>>2)+3] & ~0x3ff8) | bc; /* get new PSD 2 w/old cpix */
PSD2 = (M[(tvl>>2)+3] & ~0x3fff) | bc; /* get new PSD 2 w/old cpix */
M[(tvl>>2)+4] = TRAPSTATUS; /* store trap status */
if (TRAPME == DEMANDPG_TRAP) { /* 0xC4 Demand Page Fault Trap (V6&V9 Only) */
M[(tvl>>2)+5] = pfault; /* store page fault number */
@ -7221,12 +7228,15 @@ t_stat cpu_reset(DEVICE *dptr)
SPAD[0xff] = 0x00ffffff; /* interrupt level 7f 1's complament */
}
/* set low memory bootstrap code */
#if 0
/* mode to boot code in sel32_chan.c so we can reset system and not destroy memory */
M[0] = 0x02000000; /* 0x00 IOCD 1 read into address 0 */
M[1] = 0x60000078; /* 0x04 IOCD 1 CMD Chain, Suppress incor length, 120 bytes */
M[2] = 0x53000000; /* 0x08 IOCD 2 BKSR or RZR to re-read boot code */
M[3] = 0x60000001; /* 0x0C IOCD 2 CMD chain,Supress incor length, 1 byte */
M[4] = 0x02000000; /* 0x10 IOCD 3 Read into address 0 */
M[5] = 0x000006EC; /* 0x14 IOCD 3 Read 0x6EC bytes */
#endif
loading = 0; /* not loading yet */
/* we are good to go or error from device setup */
if (devs != SCPE_OK)

54
SEL32/sel32_disk.c
View File

@ -761,6 +761,16 @@ loop:
chp->chan_caw = (chp->chan_caw & 0xfffffc) + 8; /* point to next IOCD */
chp->ccw_cmd = (word1 >> 24) & 0xff; /* set command from IOCD wd 1 */
/* Check if we had data chaining in previous iocd */
/* if we did, use previous cmd value */
if (((chp->chan_info & INFO_SIOCD) == 0) && /* see if 1st IOCD in channel prog */
(chp->ccw_flags & FLAG_DC)) { /* last IOCD have DC set? */
sim_debug(DEBUG_CMD, dptr,
"ec_iocl @%06x DO DC, ccw_flags %04x cmd %02x\n",
chp->chan_caw, chp->ccw_flags, chp->ccw_cmd);
} else
chp->ccw_cmd = (word1 >> 24) & 0xff; /* set new command from IOCD wd 1 */
if (!MEM_ADDR_OK(word1 & MASK24)) { /* see if memory address invalid */
chp->chan_status |= STATUS_PCHK; /* bad, program check */
uptr->SNS |= SNS_INAD; /* invalid address status */
@ -861,7 +871,6 @@ loop:
return 1; /* error return */
}
#ifndef NOT_FOR_EVERYONE
/* DC can only be used with a read/write cmd */
if (chp->ccw_flags & FLAG_DC) {
if ((chp->ccw_cmd != DSK_RD) && (chp->ccw_cmd != DSK_WD)) {
@ -872,7 +881,6 @@ loop:
return 1; /* error return */
}
}
#endif
chp->chan_byte = BUFF_BUSY; /* busy & no bytes transferred yet */
@ -1569,9 +1577,6 @@ iha_error:
sim_debug(DEBUG_CMD, dptr,
"disk_srv STAR unit=%02x star %02x %02x %02x %02x\n",
unit, buf[0], buf[1], buf[2], buf[3]);
// sim_debug(DEBUG_DETAIL, dptr,
// "disk_srv seek unit=%02x star %02x %02x %02x %02x\n",
// unit, buf[0], buf[1], buf[2], buf[3]);
/* save STAR (target sector) data in STAR */
uptr->STAR = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | (buf[3]);
@ -1620,11 +1625,6 @@ iha_error:
/* calc the new sector address of data */
/* calculate file position in bytes of requested sector */
/* file offset in bytes */
//29 tstart = STAR2SEC(uptr->STAR, SPT(type), SPC(type)) * SSB(type);
/* set new STAR value using old cyl value */
// uptr->CHS = CHS2STAR(STAR2CYL(uptr->CHS), trk, buf[3]);
/* set new STAR value using new values */
/*05*/ uptr->STAR = CHS2STAR(cyl, trk, sec);
/* file offset in bytes to std or alt track */
@ -1910,10 +1910,10 @@ iha_error:
"disk_srv after READ chsa %04x buffer %06x count %04x\n",
chsa, chp->ccw_addr, chp->ccw_count);
sim_debug(DEBUG_CMD, dptr,
"disk_srv after READ buffer %06x count %04x data %02x%02x%02x%02x %02x%02x%02x%02x\n",
// chp->ccw_addr, chp->ccw_count, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]);
chp->ccw_addr, chp->ccw_count, buf[1016], buf[1017], buf[1018], buf[1019],
buf[1020], buf[1021], buf[1022], buf[1023]);
"hsdp_srv READ data %02x%02x%02x%02x %02x%02x%02x%02x "
"%02x%02x%02x%02x %02x%02x%02x%02x\n",
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
buf[8], buf[9], buf[10], buf[11], buf[12], buf[13], buf[14], buf[15]);
uptr->CHS++; /* next sector number */
/* process the next sector of data */
@ -2137,11 +2137,13 @@ iha_error:
}
sim_debug(DEBUG_CMD, dptr,
"disk_srv after WRITE buffer %06x count %04x data %02x%02x%02x%02x %02x%02x%02x%02x\n",
// chp->ccw_addr, chp->ccw_count,
// buf2[0], buf2[1], buf2[2], buf2[3], buf2[4], buf2[5], buf2[6], buf2[7]);
chp->ccw_addr, chp->ccw_count, buf2[1016], buf2[1017], buf2[1018], buf2[1019],
buf2[1020], buf2[1021], buf2[1022], buf2[1023]);
"hsdp_srv after WRITE buffer %06x count %04x\n",
chp->ccw_addr, chp->ccw_count);
sim_debug(DEBUG_CMD, dptr,
"hsdp_srv WRITE data %02x%02x%02x%02x %02x%02x%02x%02x "
"%02x%02x%02x%02x %02x%02x%02x%02x\n",
buf2[0], buf2[1], buf2[2], buf2[3], buf2[4], buf2[5], buf2[6], buf2[7],
buf2[8], buf2[9], buf2[10], buf2[11], buf2[12], buf2[13], buf2[14], buf2[15]);
sim_debug(DEBUG_CMD, dptr,
"disk_srv after WRITE CAP %06x DIAG %06x\n",
CAP(type), (((CYL(type) - 3) * HDS(type)) * SPT(type))); /* diag start */
@ -3096,8 +3098,7 @@ t_stat disk_attach(UNIT *uptr, CONST char *file)
"Disk %s cyl %d hds %d sec %d ssiz %d capacity %d\n",
disk_type[type].name, disk_type[type].cyl, disk_type[type].nhds,
disk_type[type].spt, ssize, uptr->capac); /* disk capacity */
printf(
"Disk %s cyl %d hds %d sec %d ssiz %d capacity %d\r\n",
printf("Disk %s cyl %d hds %d sec %d ssiz %d capacity %d\r\n",
disk_type[type].name, disk_type[type].cyl, disk_type[type].nhds,
disk_type[type].spt, ssize, uptr->capac); /* disk capacity */
@ -3121,8 +3122,7 @@ t_stat disk_attach(UNIT *uptr, CONST char *file)
j = (CAP(type) - (s/ssize)); /* get # sectors to write */
sim_debug(DEBUG_CMD, dptr,
"Disk attach for MPX 1.X needs %04d more sectors added to disk\n", j);
printf(
"Disk attach for MPX 1.X needs %04d more sectors added to disk\r\n", j);
printf("Disk attach for MPX 1.X needs %04d more sectors added to disk\r\n", j);
/* must be MPX 1.X disk, extend to MPX 3.X size */
/* write sectors of zero to end of disk to fill it out */
for (i=0; i<j; i++) {
@ -3171,7 +3171,7 @@ add_size:
/* seek last sector of disk */
if ((sim_fseek(uptr->fileref, (CAP(type))*ssize, SEEK_SET)) != 0) {
sim_debug(DEBUG_CMD, dptr, "Disk attach SEEK last sector failed\n");
printf( "Disk attach SEEK last sector failed\r\n");
printf("Disk attach SEEK last sector failed\r\n");
goto fmt;
}
s = ftell(uptr->fileref); /* get current file position */
@ -3196,8 +3196,7 @@ add_size:
sim_debug(DEBUG_CMD, dptr,
"Disk format error buf0 %02x buf1 %02x buf2 %02x buf3 %02x\n",
buff[0], buff[1], buff[2], buff[3]);
printf(
"Disk format error buf0 %02x buf1 %02x buf2 %02x buf3 %02x\r\n",
printf("Disk format error buf0 %02x buf1 %02x buf2 %02x buf3 %02x\r\n",
buff[0], buff[1], buff[2], buff[3]);
fmt:
/* format the drive */
@ -3222,8 +3221,7 @@ ldone:
sim_debug(DEBUG_CMD, dptr,
"File %s attached to %s creating labels\n",
file, disk_type[type].name);
printf(
"File %s attached to %s creating labels\r\n",
printf("File %s attached to %s creating labels\r\n",
file, disk_type[type].name);
i = disk_label(uptr); /* label disk */
if (i != 0) {

13
SEL32/sel32_ec.c
View File

@ -388,7 +388,6 @@ loop:
chp->chan_caw = (chp->chan_caw & 0xfffffc) + 8; /* point to next IOCD */
#ifndef NOT_HERE
/* Check if we had data chaining in previous iocd */
/* if we did, use previous cmd value */
if (((chp->chan_info & INFO_SIOCD) == 0) && /* see if 1st IOCD in channel prog */
@ -396,16 +395,8 @@ loop:
sim_debug(DEBUG_CMD, dptr,
"ec_iocl @%06x DO DC, ccw_flags %04x cmd %02x\n",
chp->chan_caw, chp->ccw_flags, chp->ccw_cmd);
// chp->ccw_flags = (word2 >> 16) & 0xf800;/* get flags from bits 0-4 of WD 2 of IOCD */
// if (chp->ccw_cmd == EC_READ) /* Force SLI on READ */
// chp->ccw_flags |= FLAG_SLI;
// chp->ccw_count = word2 & 0xffff; /* get 16 bit byte count from IOCD WD 2 */
// return 0;
} else
chp->ccw_cmd = (word1 >> 24) & 0xff; /* set new command from IOCD wd 1 */
#else
chp->ccw_cmd = (word1 >> 24) & 0xff; /* set command from IOCD wd 1 */
#endif
chp->ccw_count = 0;
if (!MEM_ADDR_OK(word1 & MASK24)) { /* see if memory address invalid */
@ -942,7 +933,7 @@ wr_end:
pck = (uint8 *)(&ec_data.rec_buff[ec_data.xtr_ptr].msg[0]);
len = (int)(ec_data.rec_buff[ec_data.xtr_ptr].len);
if (len < ec_data.conf[9]) {
sim_debug(DEBUG_DETAIL, &ec_dev, "ec_srv short read size %x %x %x\n",chp->ccw_count, i, ec_data.conf[9]);
sim_debug(DEBUG_DETAIL, &ec_dev, "ec_srv short read size %x %x\n",chp->ccw_count, ec_data.conf[9]);
ec_data.xtr_ptr = (ec_data.xtr_ptr + 1) & 0xf;
chp->ccw_count = 0;
/* diags wants prog check instead of unit check */
@ -1162,8 +1153,6 @@ wr_end:
"ec_startcmd CMD sense excess cnt %02x\n", chp->ccw_count);
break;
}
/*JB*/ ec_data.rec_buff[ec_data.xtr_ptr].len = 0; /* reset last buffer length */
uptr->SNS &= ~(SNS_CMDREJ|SNS_EQUCHK); /* clear old status */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* done */

808
SEL32/sel32_hsdp.c
View File

File diff suppressed because it is too large Load Diff

6
SEL32/sel32_mt.c
View File

@ -645,7 +645,8 @@ t_stat mt_srv(UNIT *uptr)
break;
case MT_READ: /* 0x02 */ /* read a record from the device */
sim_debug(DEBUG_DETAIL, &mta_dev, "mt_srv cmd 2 READ unit=%02x\n", unit);
// sim_debug(DEBUG_DETAIL, &mta_dev, "mt_srv cmd 2 READ unit=%02x\n", unit);
sim_debug(DEBUG_CMD, &mta_dev, "mt_srv cmd 2 READ unit=%02x\n", unit);
if (uptr->CMD & MT_READDONE) { /* is the read complete */
uptr->SNS &= ~(SNS_LOAD|SNS_EOT); /* reset BOT & EOT */
if (sim_tape_eot(uptr)) { /* see if at EOM */
@ -703,13 +704,14 @@ t_stat mt_srv(UNIT *uptr)
mt_busy[bufnum] &= ~1; /* set not busy */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* return end status */
} else {
// sim_debug(DEBUG_CMD, &mta_dev,
sim_debug(DEBUG_DETAIL, &mta_dev,
"Read data @2 unit %02x cnt %04x ch %02x hwm %04x\n",
unit, uptr->POS, ch, uptr->hwmark);
if ((uint32)uptr->POS >= uptr->hwmark) { /* In IRG */
/* Handle end of data record */
sim_debug(DEBUG_CMD, &mta_dev,
"Read too much data unit %02x cnt %04x ch %02x hwm %04x\n",
"Read end of data unit %02x cnt %04x ch %02x hwm %04x\n",
unit, uptr->POS, ch, uptr->hwmark);
uptr->CMD |= MT_READDONE; /* read is done */
sim_activate(uptr, 40); /* wait again */

10
SEL32/sel32_scfi.c
View File

@ -477,6 +477,16 @@ loop:
chp->chan_caw = (chp->chan_caw & 0xfffffc) + 8; /* point to next IOCD */
chp->ccw_cmd = (word1 >> 24) & 0xff; /* set command from IOCD wd 1 */
/* Check if we had data chaining in previous iocd */
/* if we did, use previous cmd value */
if (((chp->chan_info & INFO_SIOCD) == 0) && /* see if 1st IOCD in channel prog */
(chp->ccw_flags & FLAG_DC)) { /* last IOCD have DC set? */
sim_debug(DEBUG_CMD, dptr,
"ec_iocl @%06x DO DC, ccw_flags %04x cmd %02x\n",
chp->chan_caw, chp->ccw_flags, chp->ccw_cmd);
} else
chp->ccw_cmd = (word1 >> 24) & 0xff; /* set new command from IOCD wd 1 */
if (!MEM_ADDR_OK(word1 & MASK24)) { /* see if memory address invalid */
chp->chan_status |= STATUS_PCHK; /* bad, program check */
uptr->SNS |= SNS_INAD; /* invalid address status */

76
SEL32/sel32_scsi.c
View File

@ -177,7 +177,7 @@ bits 24-31 - FHD head count (number of heads on FHD or number head on FHD option
#define DSK_TCMD 0xD3 /* Transfer Command Packet (specifies CDB to send) */
//#define DSK_ICH 0xFF /* Initialize Controller */
#define DSK_FRE 0xF3 /* Reserved */
#define DSK_SID 0x80 /* MFP stataus command */
#define DSK_SID 0x80 /* MFP status command */
#define STAR u4
/* u4 - sector target address register (STAR) */
@ -445,46 +445,39 @@ uint16 scsi_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
if ((uptr->CMD & 0xff00) != 0) { /* if any status info, we are busy */
return SNS_BSY;
}
sim_debug(DEBUG_CMD, dptr, "scsi_startcmd CMD 2 unit=%02x cmd %02x\n", unit, cmd);
sim_debug(DEBUG_CMD, dptr, "scsi_startcmd enter unit=%02x cmd %02x\n", unit, cmd);
/* Unit is online, so process a command */
switch (cmd) {
case DSK_INCH: /* INCH 0x00 */
#ifdef DO_DYNAMIC_DEBUG
cpu_dev.dctrl |= (DEBUG_INST | DEBUG_CMD | DEBUG_EXP | DEBUG_IRQ | DEBUG_XIO);
// cpu_dev.dctrl |= (DEBUG_INST | DEBUG_CMD | DEBUG_EXP | DEBUG_IRQ | DEBUG_XIO);
#endif
sim_debug(DEBUG_CMD, dptr,
"scsi_startcmd starting INCH %06x cmd, chsa %04x MemBuf %08x cnt %04x\n",
uptr->u4, chsa, chp->ccw_addr, chp->ccw_count);
uptr->CMD |= DSK_INCH2; /* use 0xF0 for inch, just need int */
// sim_activate(uptr, 20); /* start things off */
/* leave the TCMD bit */
uptr->SNS &= ~MASK24; /* clear all but old mode data */
sim_activate(uptr, 100); /* start things off */
return 0;
break;
case DSK_RCAP: /* Read Capacity 0x53 */
uptr->CMD |= cmd; /* save cmd */
sim_debug(DEBUG_CMD, dptr,
"scsi_startcmd starting disk RCAP cmd %02x chsa %04x\n", cmd, chsa);
// sim_activate(uptr, 200); /* start things off */
sim_activate(uptr, 100); /* start things off */
// sim_activate(uptr, 20); /* start things off */
return 0;
break;
case DSK_SCK: /* Seek command 0x07 */
case DSK_XEZ: /* Rezero & Read IPL record 0x1f */
case DSK_WD: /* Write command 0x01 */
case DSK_RD: /* Read command 0x02 */
case DSK_LMR: /* read mode register */
case DSK_NOP: /* NOP 0x03 */
case DSK_SNS: /* Sense 0x04 */
// case DSK_RCAP: /* Read Capacity 0x53 */
case DSK_RCAP: /* Read Capacity 0x53 */
/* Transfer Command Packet (specifies CDB to send) */
case DSK_TCMD: /* Transfer command packet 0xD3 */
case DSK_SID: /* channel Sense 0x80 */
/* leave the TCMD bit */
uptr->SNS &= ~MASK24; /* clear all but old mode data */
case DSK_SNS: /* Sense 0x04 */
uptr->CMD |= cmd; /* save cmd */
sim_debug(DEBUG_CMD, dptr,
"scsi_startcmd starting disk seek r/w cmd %02x chsa %04x\n", cmd, chsa);
@ -644,7 +637,9 @@ t_stat scsi_srv(UNIT *uptr)
chan_write_byte(chsa, &ch);
/* bytes 4 - mode reg, byte 0 of SNS */
ch = (uptr->SNS >> 24) & 0xff; /* return the sense data */
// ch = (uptr->SNS >> 24) & 0xff; /* return the sense data */
/* skip the TCMD bit */
ch = (uptr->SNS >> 24) & 0xfe; /* return the sense data */
sim_debug(DEBUG_DETAIL, dptr, "scsi_srv sense unit=%02x 1 %02x\n",
unit, ch);
chan_write_byte(chsa, &ch);
@ -820,12 +815,16 @@ t_stat scsi_srv(UNIT *uptr)
sim_debug(DEBUG_CMD, dptr, "Load Mode Reg unit=%02x old %x new %x\n",
unit, (uptr->SNS)&0xff, buf[0]);
uptr->CMD &= LMASK; /* remove old cmd */
uptr->SNS &= MASK24; /* clear old mode data */
uptr->SNS |= (buf[0] << 24); /* save mode value */
// uptr->SNS &= MASK24; /* clear old mode data */
/* leave the TCMD bit */
uptr->SNS &= (MASK24 | SNS_TCMD); /* clear old mode data */
// uptr->SNS |= (buf[0] << 24); /* save mode value */
/* do not change TCMD bit */
uptr->SNS |= ((buf[0]&0xfe) << 24); /* save mode value */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND);
break;
case DSK_RD: /* Read Data */
case DSK_RD: /* 0x02 Read Data */
if (uptr->SNS & SNS_TCMD) {
/* we need to process a read TCMD data */
int cnt = scsi_buf[bufnum][unit][4]; /* byte count of status to send */
@ -833,9 +832,11 @@ t_stat scsi_srv(UNIT *uptr)
uint32 spt = SPT(type); /* sectors per track */
uint32 ssb = SSB(type); /* sector size in bytes */
int bcnt;
/* cnt has # bytes to return (0xf0) */
uint8 pagecode = scsi_buf[bufnum][unit][2] & 0x3f; /* get page code */
uint8 pagecont = (scsi_buf[bufnum][unit][2] & 0xc0) >> 6; /* get page control */
ch = scsi_buf[bufnum][unit][0]; /* return TCMD cmd */
uptr->SNS &= ~SNS_TCMD; /* show not presessing TCMD cmd chain */
sim_debug(DEBUG_CMD, dptr,
@ -954,6 +955,22 @@ t_stat scsi_srv(UNIT *uptr)
buf[9] = (uint8)HDS(type); /* # of heads */
goto merge; /* go output data and return */
}
case 0x12: /* inquiry */
/* size is 0x24 = 36 bytes */
/* ssize has sector size in bytes */
for (i=0; i<cnt; i++) {
buf[i] = 0; /* clear buffer */
}
/* set some sense data from SH.DCSCI driver code */
buf[0] = 0xf0; /* page length */
buf[4] = 0x81; /* savable and page type 1 */
buf[8] = 0x91;
buf[12] = 0xf4;
buf[17] = (uint8)HDS(type); /* # of heads */
buf[23] = (uint8)SPT(type); /* Sect/track */
// buf[27] = SPT(type); /* Sect/track */
merge:
/* output response data */
for (i=0; i<cnt; i++) {
@ -1210,6 +1227,7 @@ read_cap: /* merge point from TCMD process
uptr->CMD &= LMASK; /* remove old status bits & cmd */
uptr->SNS |= SNS_CMDREJ|SNS_EQUCHK;
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
return SCPE_OK;
break;
}
}
@ -1221,6 +1239,7 @@ read_cap: /* merge point from TCMD process
uptr->CMD &= LMASK; /* remove old status bits & cmd */
uptr->SNS |= SNS_CMDREJ|SNS_EQUCHK;
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
return SCPE_OK;
break;
}
}
@ -1231,7 +1250,7 @@ read_cap: /* merge point from TCMD process
"scsi_srv cmd RCAP chsa %04x capacity %06x secsize %03x completed\n",
chsa, cap, ssize);
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* return OK */
return SCPE_OK;
// return SCPE_OK;
break;
/* Transfer Command Packet (specifies CDB to send) */
@ -1269,6 +1288,7 @@ read_cap: /* merge point from TCMD process
uptr->CMD &= LMASK; /* remove old status bits & cmd */
uptr->SNS |= SNS_CMDREJ|SNS_EQUCHK;
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
return SCPE_OK;
break;
}
}
@ -1320,7 +1340,7 @@ void scsi_ini(UNIT *uptr, t_bool f)
uptr->CHS = 0; /* set CHS to cyl/hd/sec = 0 */
uptr->STAR = 0; /* set STAR to cyl/hd/sec = 0 */
uptr->CMD &= LMASK; /* remove old status bits & cmd */
uptr->SNS = ((uptr->SNS & MASK24) | (scsi_type[i].type << 24)); /* save mode value */
uptr->SNS = 0; /* clear any status */
/* total sectors on disk */
uptr->capac = CAP(i); /* disk size in sectors */
@ -1565,6 +1585,7 @@ t_stat scsi_attach(UNIT *uptr, CONST char *file) {
uint32 ssize; /* sector size in bytes */
uint8 buff[1024];
uptr->SNS = 0; /* clear any status */
if (scsi_type[type].name == 0) { /* does the assigned disk have a name */
detach_unit(uptr); /* no, reject */
return SCPE_FMT; /* error */
@ -1577,7 +1598,10 @@ t_stat scsi_attach(UNIT *uptr, CONST char *file) {
uptr->capac = CAP(type); /* disk capacity in sectors */
ssize = SSB(type); /* get sector size in bytes */
sim_debug(DEBUG_CMD, dptr, "Disk %s %04x cyl %d hds %d sec %d ssiz %d capacity %d\n",
sim_debug(DEBUG_CMD, dptr, "SCSI Disk %s %04x cyl %d hds %d sec %d ssiz %d capacity %d\n",
scsi_type[type].name, chsa, scsi_type[type].cyl, scsi_type[type].nhds,
scsi_type[type].spt, ssize, uptr->capac); /* disk capacity */
printf("SCSI Disk %s %04x cyl %d hds %d sec %d ssiz %d capacity %d\r\n",
scsi_type[type].name, chsa, scsi_type[type].cyl, scsi_type[type].nhds,
scsi_type[type].spt, ssize, uptr->capac); /* disk capacity */
@ -1617,8 +1641,14 @@ fmt:
scsi_type[type].name, chsa, CYL(type), HDS(type), SPT(type), SPC(type),
CAP(type), CAPB(type));
printf("Attach %s %04x cyl %d hds %d spt %d spc %d cap sec %d cap bytes %d\r\n",
scsi_type[type].name, chsa, CYL(type), HDS(type), SPT(type), SPC(type),
CAP(type), CAPB(type));
sim_debug(DEBUG_CMD, dptr, "File %s at chsa %04x attached to %s\n",
file, chsa, scsi_type[type].name);
printf("File %s at chsa %04x attached to %s\r\n",
file, chsa, scsi_type[type].name);
/* check for valid configured disk */
/* must have valid DIB and Channel Program pointer */