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https://github.com/rcornwell/sims.git
synced 2026-05-01 13:57:34 +00:00
B5500: Cleanup some instruction execution to better match flowcharts.
This commit is contained in:
@@ -926,7 +926,7 @@ void initiate() {
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/* Save processor state in case of error or halt */
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void storeInterrupt(int forced, int test) {
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int f;
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t_uint64 temp;
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uint16 temp;
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if (forced || test)
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NCSF = 0;
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@@ -946,7 +946,7 @@ void storeInterrupt(int forced, int test) {
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}
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/* Make ILCW */
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B = X | ((i)? PRESENT : 0) | FLAG | DFLAG;
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next_addr(S); /* Save B */
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next_addr(S); /* Save B */
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memory_cycle(11);
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} else {
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if (BROF || test) { /* Push B First */
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@@ -959,11 +959,11 @@ void storeInterrupt(int forced, int test) {
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}
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}
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AROF = 0;
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B = ICW; /* Set ICW into B */
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next_addr(S); /* Save B */
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B = ICW; /* Set ICW into B */
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next_addr(S); /* Save B */
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memory_cycle(11);
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B = RCW(f); /* Save IRCW */
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next_addr(S); /* Save B */
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B = RCW(f); /* Save IRCW */
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next_addr(S); /* Save B */
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memory_cycle(11);
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if (CWMF) {
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/* Get the correct value of R */
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@@ -1985,7 +1985,7 @@ sim_instr(void)
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int i;
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int j;
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reason = 0;
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reason = SCPE_OK;
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hltf[0] = 0;
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hltf[1] = 0;
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P1_run = 1;
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@@ -1993,17 +1993,17 @@ sim_instr(void)
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while (reason == 0) { /* loop until halted */
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if (P1_run == 0)
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return SCPE_STOP;
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/* System is booting, wait until finished loading */
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while (loading) {
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reason = sim_process_event();
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if (reason != SCPE_OK) {
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if (reason != SCPE_OK)
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break; /* process */
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}
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}
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/* Passed time quantum */
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if (sim_interval <= 0) { /* event queue? */
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reason = sim_process_event();
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if (reason != SCPE_OK) {
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if (reason != SCPE_OK)
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break; /* process */
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}
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}
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if (sim_brk_summ) {
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@@ -2178,17 +2178,12 @@ crf_loop:
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Ma = (F - field) & CORE;
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memory_cycle(4);
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AROF = 0;
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if (A & FLAG) {
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if ((A & PRESENT) == 0) {
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if (NCSF)
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Q |= PRES_BIT;
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break;
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}
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GH = 0;
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} else {
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GH = (A >> 12) & 070;
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}
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Ma = CF(A);
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GH = 0;
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if ((A & FLAG) == 0)
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GH = (A >> 12) & 070;
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else if ((A & PRESENT) == 0 && NCSF)
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Q |= PRES_BIT;
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break;
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case CMOP_RDA: /* Recall Destination Address */
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@@ -2197,34 +2192,29 @@ crf_loop:
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S = (F - field) & CORE;
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memory_cycle(3);
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BROF = 0;
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if (B & FLAG) {
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if ((B & PRESENT) == 0) {
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if (NCSF)
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Q |= PRES_BIT;
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break;
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}
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KV = 0;
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} else {
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KV = (B >> 12) & 070;
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}
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S = CF(B);
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KV = 0;
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if ((B & FLAG) == 0)
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KV = (B >> 12) & 070;
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else if ((B & PRESENT) == 0 && NCSF)
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Q |= PRES_BIT;
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break;
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case CMOP_RCA: /* Recall Control Address */
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AROF = BROF;
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A = B; /* Save B temporarly */
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A = B; /* Save B temporarly */
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atemp = S; /* Save S */
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S = (F - field) & CORE;
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memory_cycle(3); /* Load word in B */
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memory_cycle(3);/* Load word in B */
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S = atemp; /* Restore S */
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if (B & FLAG) {
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if ((B & PRESENT) == 0) {
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if (NCSF)
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Q |= PRES_BIT;
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break;
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} else {
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C = CF(B);
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L = 0;
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}
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C = CF(B);
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L = 0;
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} else {
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C = CF(B);
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L = LF(B) + 1;
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@@ -2312,9 +2302,10 @@ crf_loop:
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A = B;
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AROF = BROF;
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B = ((t_uint64)(KV & 070) << (FFIELD_V - 3)) | toC(S);
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atemp = S;
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S = (F - field) & CORE;
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memory_cycle(013); /* Store B in S */
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S = CF(B);
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S = atemp;
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B = A;
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BROF = AROF;
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AROF = 0;
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@@ -2325,9 +2316,10 @@ crf_loop:
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A = B;
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AROF = BROF;
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B = ((t_uint64)(GH & 070) << (FFIELD_V - 3)) | toC(Ma);
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atemp = Ma;
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Ma = (F - field) & CORE;
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memory_cycle(015); /* Store B in Ma */
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Ma = CF(B);
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Ma = atemp;
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B = A;
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BROF = AROF;
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AROF = 0;
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@@ -3672,17 +3664,12 @@ control:
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R = 0;
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F = S; /* Set F and X */
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X = toF(S);
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if (B & FLAG) {
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if ((B & PRESENT) == 0) {
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if (NCSF)
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Q |= PRES_BIT;
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break;
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}
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KV = 0;
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} else {
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KV = (uint8)((B >> (FFIELD_V - 3)) & 070);
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}
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S = CF(B);
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KV = 0;
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if ((B & FLAG) == 0)
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KV = (uint8)((B >> (FFIELD_V - 3)) & 070);
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else if ((B & PRESENT) == 0 && NCSF)
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Q |= PRES_BIT;
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break;
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case VARIANT(WMOP_MKS): /* Mark Stack */
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